rominit.s

cpc-1631的BSP包for VxWorks操作系统

#define MC1_BURST			0		/* 0-1 *//*?*/
#define MC1_MEMGO			0		/* 0-1 */
#define MC1_SREN			1		/* 0-1 */    /*?*/
#define MC1_RAM_TYPE		0		/* 0-1 */
#define MC1_PCKEN			MC_ECC		/* 0-1 */
#define MC1_BANKBITS		0x0000		/* 2 bits/bank 7-0 */

	LOADPTR (r3, MPC107_MCCR1_ADRS)	/* Set MCCR1 (F0) */
	stwbrx	r3,0,r5
	LOADPTR(r4, \
		MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \
		MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \
		MC1_MEMGO << 19 | MC1_SREN << 18 | \
		MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 | \
		MC1_BANKBITS)
	stwbrx	r4, 0, r6

	/*------- MCCR2 */

#define MC2_TS_WAIT_TIMER		0		/* 0-7 */
#define MC2_ASRISE			10/*2*/		/* 0-15 clock*/
#define MC2_ASFALL			10/*2*/		/* 0-15 clock*/
#define MC2_INLINE_PAR_NOT_ECC		0		/* 0-1 */
#define MC2_WRITE_PARITY_CHK_EN		MC_ECC		/* 0-1 */
#define MC2_INLRD_PARECC_CHK_EN		MC_ECC		/* 0-1 */
#define MC2_ECC_EN			0		/* 0-1 */
#define MC2_EDO				0		/* 0-1 */
#define MC2_REFINT			0x133		/* 0-0x3fff */
#define MC2_RSV_PG			0		/* 0-1 */
#define MC2_RMW_PAR			MC_ECC		/* 0-1 */

	LOADPTR (r3, MPC107_MCCR2_ADRS)	/* Set MCCR2 (F4) */
	stwbrx	r3,0,r5
	LOADPTR(r4, \
		MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \
		MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \
		MC2_WRITE_PARITY_CHK_EN << 19 | \
		MC2_INLRD_PARECC_CHK_EN << 18 | \
		MC2_ECC_EN << 17 | MC2_EDO << 16 | \
		MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
	stwbrx	r4,0,r6

	/*------- MCCR3 */

#define MC3_BSTOPRE_U			7               /* 0-15 */
#define MC3_REFREC			8		/*	 0-15 */
#define MC3_RDLAT			0       /*imax-czh (4+MC_ECC)	 0-15 */
#define MC3_CPX				0		/* 0-1 */
#define MC3_RAS6P			0		/* 0-15 */
#define MC3_CAS5			0		/* 0-7 */
#define MC3_CP4				0		/* 0-7 */
#define MC3_CAS3			0		/* 0-7 */
#define MC3_RCD2			0		/* 0-7 */
#define MC3_RP1				0		/* 0-7 */

	LOADPTR (r3, MPC107_MCCR3_ADRS)	/* Set MCCR3 (F8) */
	stwbrx	r3,0,r5
	LOADPTR(r4, \
		MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \
		MC3_RDLAT << 20 | MC3_CPX << 19 | \
		MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
		MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
	stwbrx	r4,0,r6

	/*------- MCCR4 */

#define MC4_PRETOACT		5/*3*/	/*		 0-15 */
#define MC4_ACTOPRE			7/*5*/		/* 0-15 */
#define MC4_WMODE			0		/* 0-1 */
#define MC4_INLINE			MC_ECC		/* 0-1 */
#define MC4_DBUS            1      /* 64bit bus */ 
#define MC4_EXTROM          1      /* extrom support*/ 
#define MC4_REGISTERED			(1-MC_ECC)	/* 0-1 */
#define MC4_BSTOPRE_UU			0               /* 0-3 */
#define MC4_REGDIMM			0		/* 0-1 */
#define MC4_SDMODE_CAS			3		/* 0-7 */
#define MC4_SDMODE_WRAP			0		/* 0-1 */
#define MC4_SDMODE_BURST		2		/* 0-7 */
#define MC4_ACTORW				5/*3*/      /*0-15 */
#define MC4_BSTOPRE_L			9               /* 0-16 */

	LOADPTR (r3, MPC107_MCCR4_ADRS)	/* Set MCCR4 (FC) */
	stwbrx	r3,0,r5
	LOADPTR(r4, \
		MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \
		MC4_WMODE << 23 | MC4_INLINE << 22 | \
		MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \
		MC4_DBUS << 17 | MC4_EXTROM << 21  | \
		MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
		MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
		MC4_ACTORW << 4 | MC4_BSTOPRE_L)
	stwbrx	r4,0,r6

#ifdef INCLUDE_ECC
	/*------- MEM_ERREN1 */

	LOADPTR (r3, MEM_ERREN1_ADR)	/* Set MEM_ERREN1 (c0) */
	stwbrx	r3,0,r5
	lwbrx	r4,0,r6
	ori	r4,r4,4			/* Set MEM_PERR_EN */
	stwbrx	r4,0,r6
#endif /* INCLUDE_ECC */

	LOADPTR (r3, MEM_AMBOR_ADR)	/* imax-czh Set AMBOR (0xe0) */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0xbc7800c0/*0xa87800c0*/)
	stwbrx	r4,0,r6

	/*------- PCI*CLK */

	LOADPTR (r3, PCI_CLK_REG)	/* Set PCI*CLK (74) */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0x30020300/*0x10040300*/)
	stwbrx	r4,0,r6

	/*------- MSAR/MEAR */
	/*
	Memory
	bank 0 :0x00000000-0x07ffffff(128M) ---CS0
	bank 1 :0x08000000-0x0fffffff(128M) ---CS1
	bank 2 :0x10000000-0x17ffffff(128M) ---CS2
	bank 3 :0x18000000-0x1fffffff(128M) ---CS3
	*/
	
	LOADPTR (r3, MPC107_MSAR1_ADRS)	/* Set MSAR1 (80) */
	stwbrx	r3,0,r5
	LOADPTR (r4, MPC107_MSAR1_VAL)
	stwbrx	r4,0,r6

	LOADPTR (r3, MPC107_MSAR2_ADRS)	/* Set MSAR2 (84) */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0x00000000)
	stwbrx	r4,0,r6

	LOADPTR (r3, MPC107_XMSAR1_ADRS)	/* Set MESAR1 (88) */
	stwbrx	r3,0,r5
	LOADPTR (r4, MPC107_XMSAR1_VAL)
	stwbrx	r4,0,r6

	LOADPTR (r3, MPC107_XMSAR2_ADRS)	/* Set MESAR2 (8c) */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0x00000000)
	stwbrx	r4,0,r6

	LOADPTR (r3, MPC107_MEAR1_ADRS)	/* Set MEAR1 (90) */
	stwbrx	r3,0,r5
	LOADPTR (r4, MPC107_MEAR1_VAL)
	stwbrx	r4,0,r6

	LOADPTR (r3, MPC107_MEAR2_ADRS)	/* Set MEAR2 (94) */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0x00000000)
	stwbrx	r4,0,r6

	LOADPTR (r3, MPC107_XMEAR1_ADRS)	/* MEEAR1 (98) */
	stwbrx	r3,0,r5
	LOADPTR (r4, MPC107_XMEAR1_VAL)
	stwbrx	r4,0,r6

	LOADPTR (r3, MPC107_XMEAR2_ADRS)	/* MEEAR2 (9c) */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0x00000000)
	stwbrx	r4,0,r6

	/*-------PMCR2 */

	LOADPTR (r3, PCI_PMCR2)	/* Set PMCR2 */
	stwbrx	r3,0,r5

	li	r4, 0/*0x20*/
	stb	r4, 2(r6)		/* ODCR is at +3 offset */
	
	/*-------ODCR */

	LOADPTR (r3, MPC107_ODCR_ADRS)	/* Set ODCR */
	stwbrx	r3,0,r5

	li	r4, 0x18/*0x7f*/
	stb	r4, 3(r6)		/* ODCR is at +3 offset */

	/*-------MBEN */

	LOADPTR (r3, MPC107_MBER_ADRS)	/* Set MBEN (a0) */
	stwbrx	r3,0,r5
	li	r4, MPC107_MBER_VAL		/* Enable bank 0-3*/
	stb	r4, 0(r6)		/* MBEN is at +0 offset */

#if 1  /*imax-czh*/ 
	/*-------PGMAX */
	LOADPTR (r3, MPC107_MPMR_ADRS)/* Set MPMR (a0) */
	stwbrx	r3,0,r5
	li	r4, 0x00
	stb	r4, 3(r6)		/* PAGE_MODE is at +3 offset */
#endif

	/* Wait before initializing other registers */

	lis	r4,0x0001
	mtctr	r4

KahluaX4wait200us:
	bdnz	KahluaX4wait200us

	/* Set MEMGO bit */

	LOADPTR (r3, MPC107_MCCR1_ADRS)	/* MCCR1 (F0) |= PGMAX */
	stwbrx	r3,0,r5
	lwbrx	r4,0,r6			/* old MCCR1 */
	oris	r4,r4,0x0008		/* MEMGO=1 */
	stwbrx	r4, 0, r6

	/* Wait again */

	addis	r4,r0,0x0002
	ori	r4,r4,0xffff

	mtctr	r4

KahluaX4wait8ref:
	bdnz 	KahluaX4wait8ref

	sync
	eieio

#if	FALSE	/* EABI SDA not supported yet */

	/* initialize r2 and r13 according to EABI standard */

	LOADPTR (r2, _SDA2_BASE_)
	LOADPTR (r13, _SDA_BASE_)
#endif

	/* Display a message indicating PROM has started */
#if 0 /*imax-czh*/
#define PUTC(ch)	li r3, ch; bl SEROUT

	PUTC(13)
	PUTC(10)
	PUTC(10)
	PUTC('B')
	PUTC('o')
	PUTC('o')
	PUTC('t')
	PUTC('i')
	PUTC('n')
	PUTC('g')
	PUTC('.')
	PUTC('.')
	PUTC('.')
	PUTC(13)
	PUTC(10)
	PUTC(10)
#endif

	/* go to C entry point */

	or	r3, r11, r11		/* put startType in r3 (p0) */
	addi	sp, sp, -FRAMEBASESZ	/* save one frame stack */
	
#if 1
LOOP:
/**************循环1************/
	lis	r6, HIADJ(0x00100000)
	addi	r6, r6, LO(0x00100000 )
	
LOOPA:
	lis	r4, HIADJ(0xffc00002)	
	addi	r4, r4, LO(0xffc00002)

        /*****light LED*****/
        lis     r5,HIADJ(0xbf)/*任意值*/
        addi    r5,r5,LO(0xbf)
        stwbrx   r5,0,r4
        xor     r5,r5,r5

        addi    r6,r6,-1
        cmpwi   r6,0
        bne    LOOPA
/**************循环1************/     

/**************循环2************/
	lis	r6, HIADJ(0x00010000)
	addi	r6, r6, LO(0x00010000 )
	
LOOPB:
	lis	r4, HIADJ(0xffc00002)	
	addi	r4, r4, LO(0xffc00002)

        /*****Out LED*****/
        lis     r5,HIADJ(0xff)/*任意值*/
        addi    r5,r5,LO(0xff)
        stwbrx   r5,0,r4
        xor     r5,r5,r5

        addi    r6,r6,-1
        cmpwi   r6,0
        bne    LOOPB
/**************循环2************/     

    /*bl LOOP*/
#endif	

	LOADPTR (r6, romStart)
	LOADPTR (r7, romInit)
	LOADPTR (r8, ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8

	mtlr	r6		/* romStart - romInit + ROM_TEXT_ADRS */
	blr

/**********************************************************************
 *  void SEROUT(int char);
 *
 *  Configure Mousse COM1 to 9600 baud and write a character.
 *  Should be usable basically at any time.
 *
 *  r3 = character to output
 */

SEROUT:
	/* r4 = intLock() */
	mfmsr	r4
	rlwinm	r5,r4,0,17,15
	mtmsr	r5
	isync

 	/* 
	* read the PLL register to compute the frequency.
        * Also, need to use the internal UART.  EUMBBAR must be 
        * initialized for this routine to work on bmw.
        * Regs 7-11 are available for the extra work.
        */
        
	LOADPTR (r7, MPC107_CFG_ADDR_CHRP)	
	LOADPTR (r8, MPC107_CFG_DATA_CHRP)	

	LOADPTR (r9, PLL_CFG_ADR_X)	
	stwbrx	r9,0,r7
	lbz	r9, PLL_CFG_ADR_SHIFT(r8)

        /* 
        * r9 contains PLL_VALUE || <000>b 
        * Assume PLL is such that SDRAM clock is 66 MHZ,
        * unless it's set to 85 MHz or 100 MHz (assuming 33 MHz PCI clock)
        */
#define PLL_66MHZ 0xb0
#define PLL_85MHZ 0xc0
#define PLL_100MHZ 0x80
#define PLL_75MHZ_PCI50 0xe0
#define PLL_100MHZ_PCI50 0xc8

        cmpli   0, 0, r9, PLL_85MHZ
	beq uart85
        cmpli   0, 0, r9, PLL_100MHZ
	beq uart100
        cmpli   0, 0, r9, PLL_75MHZ_PCI50
	beq uart75
        cmpli   0, 0, r9, PLL_100MHZ_PCI50
	beq uart100
        cmpli   0, 0, r9, PLL_66MHZ
	beq uart66
uart66:
	LOADPTR (r9, 434)
	b uartgo
uart85:
	LOADPTR (r9, 543)
	b uartgo
uart100:
	LOADPTR (r9, 651)
        b uartgo
uart75:
	LOADPTR (r9, 488)
        b uartgo
uartgo:

	/* r5 = serial port address, channel 0 */

	LOADPTR(r5, EUMBBAR_VAL | 0x4500)

	/* Init serial port */
	li	r6, 0x83		/* Enable divisor latch */
	stb	r6, 3(r5)
	sync
	clrlwi  r6, r9, 24
	stb	r6, 0(r5)		/* baud_lo */
	rlwinm  r6, r9, 24, 24, 31
	stb	r6, 1(r5)		/* baud_hi */
	li	r6, 0x03
	stb	r6, 3(r5)		/* 8-n-1 */
	li	r6, 0x01
	stb	r6, 0x11(r5)		/* 2-pin mode */
	
	/* Wait for transmit buffer available */
sowait:
    lbz	r6, 5(r5)
	andi.	r0, r6, 0x40
	bc	12, 2, sowait

	/* Transmit byte */
	stb	r3, 0(r5)

	/* intUnlock(r4) */
	rlwinm	r4,r4,0,16,16
	mfmsr	r5
	or	r4,r4,r5
	mtmsr	r4
	isync

    blr

/*#include "sysL2Backcache.s"*/