rominit.s

cpc-1631的BSP包for VxWorks操作系统

/* romInit.s - general PPC 603/604 ROM initialization module
 * Copyright 1984-1998 Wind River Systems, Inc.
 * Copyright 1996-1998 Motorola, Inc.


modification history
--------------------
01a,02Feb99, My  Copied from Yellowknife platform and deleted unused code.


DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.
The entry point, romInit(), is the first code executed on power-up.
It performs the minimal setup needed to call
the generic C routine romStart() with parameter BOOT_COLD.

RomInit() typically masks interrupts in the processor, sets the initial
stack pointer (to STACK_ADRS which is defined in configAll.h), and
readies system memory by configuring the DRAM controller if necessary.
Other hardware and device initialization is performed later in the
BSP's sysHwInit() routine.

A second entry point in romInit.s is called romInitWarm(). It is called
by sysToMonitor() in sysLib.c to perform a warm boot.
The warm-start entry point must be written to allow a parameter on
the stack to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"
#include "mpc107.h"


/* defines */

/*
 * Some releases of h/arch/ppc/toolPpc.h had a bad definition of
 * LOADPTR. So we will define it correctly. [REMOVE WHEN NO LONGER NEEDED].
 *
 * LOADPTR initializes a register with a 32 bit constant, presumably the
 * address of something.
 */

#undef LOADPTR
#define	LOADPTR(reg,const32) \
	  addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)


	/* Exported internal functions */

	.data
	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */
	.globl	_romInitWarm	/* start of system code */
	.globl	romInitWarm	/* start of system code */

	.globl	SEROUT		/* useful serial output routine */

	/* externals */

	.extern romStart	/* system initialization routine */

	.text
	.align 2


/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

#ifndef ROM_RESIDENT
/*  Offset 0x100  by reserving 0x100 bytes of zero before the first
 *   executable instruction so we start at
 *   the reset vector address of 0x100
 *   This allows our old DataIO ROM burner to burn the ROM's correctly,
 *   and this works for all the targets except the ROM resident targets,
 *   hence why we encapsulate this pseudop with #ifndef ROM_RESIDENT.
 *   It is also necessary to manually change the Makefile macro
 *   HEX_FLAGS to -a 100 for the ROM_RESIDENT targets.
 */
	.space (0x100)
#endif	/*  ROM_RESIDENT  */

_romInit:
romInit:

	/* This is the cold boot entry (ROM_TEXT_ADRS) */

	bl	cold

	/*
	 * This warm boot entry point is defined as ROM_WARM_ADRS in config.h.
	 * It is defined as an offset from ROM_TEXT_ADRS.  Please make sure
	 * that the offset from _romInit to romInitWarm matches that specified
	 * in config.h
	 */

_romInitWarm:
romInitWarm:
	bl	warm

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii	 "Copyright 1984-1998 Wind River Systems, Inc."
	.align 2

cold:
	li	r11, BOOT_COLD
	bl	start		/* skip over next instruction */


warm:
	or	r11, r3, r3	/* startType to r11 */

start:
	/* Zero-out registers */

	addis	r0,r0,0
	mtspr	SPRG0,r0
	mtspr	SPRG1,r0
	mtspr	SPRG2,r0
	mtspr	SPRG3,r0

	/* initialize the stack pointer */

	LOADPTR (sp, STACK_ADRS)

	/* Set MPU/MSR to a known state. Turn on FP */

	LOADPTR (r3, _PPC_MSR_FP)
	sync
	mtmsr	r3
	isync

	/* Init the floating point control/status register */

	mtfsfi	7,0x0
	mtfsfi	6,0x0
	mtfsfi	5,0x0
	mtfsfi	4,0x0
	mtfsfi	3,0x0
	mtfsfi	2,0x0
	mtfsfi	1,0x0
	mtfsfi	0,0x0
	isync

	/* Initialize the floating point data regsiters to a known state */

	bl	ifpdr_value
	.long	0x3f800000	/* 1.0 */

ifpdr_value:
	mfspr	r3,8
	lfs	f0,0(r3)
	lfs	f1,0(r3)
	lfs	f2,0(r3)
	lfs	f3,0(r3)
	lfs	f4,0(r3)
	lfs	f5,0(r3)
	lfs	f6,0(r3)
	lfs	f7,0(r3)
	lfs	f8,0(r3)
	lfs	f9,0(r3)
	lfs	f10,0(r3)
	lfs	f11,0(r3)
	lfs	f12,0(r3)
	lfs	f13,0(r3)
	lfs	f14,0(r3)
	lfs	f15,0(r3)
	lfs	f16,0(r3)
	lfs	f17,0(r3)
	lfs	f18,0(r3)
	lfs	f19,0(r3)
	lfs	f20,0(r3)
	lfs	f21,0(r3)
	lfs	f22,0(r3)
	lfs	f23,0(r3)
	lfs	f24,0(r3)
	lfs	f25,0(r3)
	lfs	f26,0(r3)
	lfs	f27,0(r3)
	lfs	f28,0(r3)
	lfs	f29,0(r3)
	lfs	f30,0(r3)
	lfs	f31,0(r3)
	sync

	/* Set MPU/MSR to a known state. Turn off FP */

#if 1	/* Code removed so FP stays on */
        andi.	r3, r3, 0
	sync
	mtmsr 	r3
	isync
#endif

	/* Init the Segment registers */

	andi.	r3, r3, 0
	isync
	mtsr	0,r3
	isync
	mtsr	1,r3
	isync
	mtsr	2,r3
	isync
	mtsr	3,r3
	isync
	mtsr	4,r3
	isync
	mtsr	5,r3
	isync
	mtsr	6,r3
	isync
	mtsr	7,r3
	isync
	mtsr	8,r3
	isync
	mtsr	9,r3
	isync
	mtsr	10,r3
	isync
	mtsr	11,r3
	isync
	mtsr	12,r3
	isync
	mtsr	13,r3
	isync
	mtsr	14,r3
	isync
	mtsr	15,r3
	isync

	/* Turn off data and instruction cache control bits */

	mfspr	r3, HID0
	isync
	rlwinm	r4, r3, 0, 18, 15	/* r4 has ICE and DCE bits cleared */
	sync
	isync
	mtspr	HID0, r4		/* HID0 = r4 */
	isync

	/* Get cpu type */

	mfspr	r28, PVR
	rlwinm	r28, r28, 16, 16, 31

	/* invalidate the MPU's data/instruction caches */

	lis	r3, 0x0
	cmpli	0, 0, r28, CPU_TYPE_603
	beq	cpuIs603
	cmpli	0, 0, r28, CPU_TYPE_603E
	beq	cpuIs603
	cmpli	0, 0, r28, CPU_TYPE_603P
	beq	cpuIs603
	cmpli	0, 0, r28, CPU_TYPE_604R
	bne	cpuNot604R

cpuIs604R:
	lis	r3, 0x0
	mtspr	HID0, r3		/* disable the caches */
	isync
	ori	r4, r4, 0x0002		/* disable BTAC by setting bit 30 */

cpuNot604R:
	ori	r3, r3, (_PPC_HID0_ICFI | _PPC_HID0_DCFI)

cpuIs603:
	ori	r3, r3, (_PPC_HID0_ICE | _PPC_HID0_DCE)
	or	r4, r4, r3		/* set bits */
	sync
	isync
	mtspr	HID0, r4		/* HID0 = r4 */
	andc 	r4, r4, r3		/* clear bits */
	isync
	cmpli	0, 0, r28, CPU_TYPE_604
	beq	cpuIs604
	cmpli	0, 0, r28, CPU_TYPE_604E
	beq	cpuIs604
	cmpli	0, 0, r28, CPU_TYPE_604R
	beq	cpuIs604
	mtspr	HID0, r4
	isync

#ifdef USER_I_CACHE_ENABLE
	b	instCacheOn603
#else
	b	cacheEnableDone
#endif

cpuIs604:
	LOADPTR (r5, 0x1000)		/* loop count, 0x1000 */
	mtspr	CTR, r5
loopDelay:
	nop
	bdnz 	loopDelay
	isync
	mtspr	HID0, r4
	isync

	/* turn the Instruction cache ON for faster FLASH ROM boots */

#ifdef USER_I_CACHE_ENABLE

	ori	r4, r4, (_PPC_HID0_ICE | _PPC_HID0_ICFI)
	isync				/* Synchronize for ICE enable */
	b	writeReg4
instCacheOn603:
	ori	r4, r4, (_PPC_HID0_ICE | _PPC_HID0_ICFI)
	rlwinm	r3, r4, 0, 21, 19	/* clear the ICFI bit */

	/*
         * The setting of the instruction cache enable (ICE) bit must be
         * preceded by an isync instruction to prevent the cache from being
         * enabled or disabled while an instruction access is in progress.
         */
	isync
writeReg4:
	mtspr	HID0, r4		/* Enable Instr Cache & Inval cache */
	cmpli	0, 0, r28, CPU_TYPE_604
	beq	cacheEnableDone
	cmpli	0, 0, r28, CPU_TYPE_604E
	beq	cacheEnableDone

	mtspr	HID0, r3		/* using 2 consec instructions */
					/* PPC603 recommendation */
#endif
cacheEnableDone:

	/* Detect map A or B */

	addis	r5,r0, HI(MPC107_CFG_ADDR_CHRP)
	addis	r6,r0, HI(MPC107_CFG_DATA_CHRP)

	LOADPTR (r7, PPMC8245_ID)		/* PPMC8245 PCI controller ID */
	LOADPTR (r8, MPC107_CFG_BASE)

	stwbrx	r8,0,(r5)
	lwbrx	r3,0,(r6)		/* Store read value to r3 */
	cmp	0,0,r3,r7
	beq	cr0, X4_KAHLUA_START

	LOADPTR (r5, MPC107_CFG_ADDR_CHRP)
	LOADPTR (r6, MPC107_CFG_DATA_CHRP)

X4_KAHLUA_START:

    LOADPTR (r3, MPC107_PCICMD_ADRS)	/* program MPC107's PCI cmd reg. */
	stwbrx	r3, 0,r5 
	sync
    li      r4,0x0006      		/* Set to 06 (Memory Space)*/
	stwbrx	r3,0,r5
	sync
	sthbrx  r4,0,r6
	sync

    
	LOADPTR (r3, MPC107_PCISTAT_ADRS)	/* Program MPC107's PCI status reg. */
	stwbrx	r3,0,r5
	li      r3, 0x0002      /* Add offset -- this register is 2 bytes */
	lhbrx   r4, r3, r6          	
	sync
	ori     r4, r4, 0xffff     	/* Clear all bits */
	sthbrx  r4, r3, r6         
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_PCI_PGCR)	/*imax-czh PCI general control reg */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0x80000000)
	stwbrx	r4,0,r6

	/*-------PICR1 adrs */
	
	LOADPTR (r3, MPC107_PICR1_ADRS)	/* Processor I/F Config 1 reg. */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0xff141b98)
	stwbrx	r4,0,r6

	/*-------PICR2 adrs */

	LOADPTR (r3, MPC107_PICR2_ADRS) 	/*imax-czh Processor I/F Config 2 reg. */
	stwbrx	r3,0,r5
	LOADPTR (r4, 0x40604/*0x20000000*/)/*?*/
	stwbrx	r4,0,r6

	/*-------MCCR1 */

#ifdef INCLUDE_ECC
#define MC_ECC				1
#else /* INCLUDE_ECC */
#define MC_ECC				0
#endif /* INCLUDE_ECC */

#define MC1_ROMNAL			7 /*8		 0-15 */
#define MC1_ROMFAL			11		/* 0-31 */
#define MC1_DBUS_SIZE		0		/* 0-3 *//*?*/