📄 sysalib.s
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/* sysALib.s - Yellowknife system-dependent assembly routines */
/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-1999 Motorola, Inc. */
/*
modification history
--------------------
01k,25mar02,pcs Add recognition of MPC7455.
01j,31jan02,pcs include sysCacheLockALib.s only if !SP8240
01i,04jan02,pcs Add 7450 L3 Cache support.
01h,31oct01,pcs Add support for 7450.
01i,22jan02,pcs Merge from T2.1
01h,21jan02,pcs Changed sysPVRReadSys to return 32 bits instead of 16 bits.
01g,17may01,pch Improvements similar to those in romInit.s of 07may01.
01f,08may01,pch Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)
01e,13apr01,mil Fixed sysPVRReadSys() to unsigned shift
01d,09apr01,mil Added detection of 7410 and bug on L2PMCR
01c,20mar01,kab auto-merge.
01c,15mar01,kxb Merge of Sekhar's mods.
01c,26jan01,pcs Add #include "sysCacheLockALib.s"
01b,28oct00,ksn removed L2 cache intialization and disabling
routines (teamF1)
01a,10oct99,mtl written from SPS/Motorola & yk 750 by teamF1
*/
/*
DESCRIPTION
This module contains the entry code, sysInit(), for VxWorks images that start
running from RAM, such as 'vxWorks'. These images are loaded into memory
by some external program (e.g., a boot ROM) and then started.
The routine sysInit() must come first in the text segment. Its job is to perform
the minimal setup needed to call the generic C
routine usrInit() with parameter BOOT_COLD.
The routine sysInit() typically masks interrupts in the processor, sets the
initial stack pointer to _sysInit then jumps to usrInit.
Most other hardware and device initialization is performed later by
sysHwInit().
*/
/* includes */
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "config.h"
#include "regs.h"
#include "asm.h"
#ifdef INCLUDE_CACHE_L2
#include "sysL2BackCache.h"
#endif
/* defines */
/*
* Some releases of h/arch/ppc/toolPpc.h had bad definitions of
* LOADPTR and LOADVAR. So we will define it correctly.
* [REMOVE THESE FOR NEXT MAJOR RELEASE].
*
* LOADPTR initializes a register with a 32 bit constant, presumably the
* address of something.
*/
#undef LOADPTR
#define LOADPTR(reg,const32) \
addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)
/*
* LOADVAR initializes a register with the contents of a specified memory
* address. The difference being that the value loaded is the contents of
* the memory location and not just the address of it.
*/
#undef LOADVAR
#define LOADVAR(reg,addr32) \
addis reg,r0,HIADJ(addr32); lwz reg,LO(addr32)(reg)
/* globals */
FUNC_EXPORT(_sysInit) /* start of system code */
FUNC_EXPORT(sysInByte)
FUNC_EXPORT(sysOutByte)
FUNC_EXPORT(sysPciRead32)
FUNC_EXPORT(sysPciWrite32)
FUNC_EXPORT(sysPciInByte)
FUNC_EXPORT(sysPciOutByte)
FUNC_EXPORT(sysPciInWord)
FUNC_EXPORT(sysPciOutWord)
FUNC_EXPORT(sysPciInLong)
FUNC_EXPORT(sysPciOutLong)
FUNC_EXPORT(sysInWord)
FUNC_EXPORT(sysOutWord)
FUNC_EXPORT(sysInLong)
FUNC_EXPORT(sysOutLong)
FUNC_EXPORT(sysMemProbeSup)
FUNC_EXPORT(sysPVRReadSys)
FUNC_EXPORT(sysSioWrite)
FUNC_EXPORT(sysSioRead)
/* externals */
FUNC_IMPORT(usrInit)
_WRS_TEXT_SEG_START
/*******************************************************************************
*
* sysInit - start after boot
*
* This is the system start-up entry point for VxWorks in RAM, the
* first code executed after booting. It disables interrupts, sets up
* the stack, and jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down from the address of sysInit(). This
* stack is used only by usrInit() and is never used again. Memory for the
* stack must be accounted for when determining the system load address.
*
* NOTE: This routine should not be called by the user.
*
* RETURNS: N/A
* sysInit (void) /@ THIS IS NOT A CALLABLE ROUTINE @/
*/
FUNC_BEGIN(_sysInit)
/* disable interrupts */
xor p0, p0, p0
mtmsr p0 /* clear the MSR register */
/* Zero-out registers: r0 & SPRGs */
xor r0,r0,r0
mtspr 272,r0
mtspr 273,r0
mtspr 274,r0
mtspr 275,r0
/*
* Set MPU/MSR to a known state
* Turn on FP
*/
andi. r3, r3, 0
ori r3, r3, 0x2000
sync
mtmsr r3
isync
sync
/* Init the floating point control/status register */
mtfsfi 7,0x0
mtfsfi 6,0x0
mtfsfi 5,0x0
mtfsfi 4,0x0
mtfsfi 3,0x0
mtfsfi 2,0x0
mtfsfi 1,0x0
mtfsfi 0,0x0
isync
/* Initialize the floating point data registers to a known state */
bl ifpdrValue
.long 0x3f800000 /* 1.0 */
ifpdrValue:
mfspr r3,LR
lfs f0,0(r3)
lfs f1,0(r3)
lfs f2,0(r3)
lfs f3,0(r3)
lfs f4,0(r3)
lfs f5,0(r3)
lfs f6,0(r3)
lfs f7,0(r3)
lfs f8,0(r3)
lfs f9,0(r3)
lfs f10,0(r3)
lfs f11,0(r3)
lfs f12,0(r3)
lfs f13,0(r3)
lfs f14,0(r3)
lfs f15,0(r3)
lfs f16,0(r3)
lfs f17,0(r3)
lfs f18,0(r3)
lfs f19,0(r3)
lfs f20,0(r3)
lfs f21,0(r3)
lfs f22,0(r3)
lfs f23,0(r3)
lfs f24,0(r3)
lfs f25,0(r3)
lfs f26,0(r3)
lfs f27,0(r3)
lfs f28,0(r3)
lfs f29,0(r3)
lfs f30,0(r3)
lfs f31,0(r3)
sync
/*
* Set MPU/MSR to a known state
* Turn off FP
*/
andi. r3, r3, 0
sync
mtmsr r3
isync
sync
/* Init the Segment registers */
andi. r3, r3, 0
isync
mtsr 0,r3
isync
mtsr 1,r3
isync
mtsr 2,r3
isync
mtsr 3,r3
isync
mtsr 4,r3
isync
mtsr 5,r3
isync
mtsr 6,r3
isync
mtsr 7,r3
isync
mtsr 8,r3
isync
mtsr 9,r3
isync
mtsr 10,r3
isync
mtsr 11,r3
isync
mtsr 12,r3
isync
mtsr 13,r3
isync
mtsr 14,r3
isync
mtsr 15,r3
isync
/* insert protection from decrementer exceptions */
xor p0, p0, p0
LOADPTR (p1, 0x4c000064) /* load rfi (0x4c000064) to p1 */
stw p1, 0x900(r0) /* store rfi at 0x00000900 */
/* initialize the stack pointer */
lis sp, HI(RAM_LOW_ADRS)
addi sp, sp, LO(RAM_LOW_ADRS)
/* Turn off data and instruction cache control bits */
mfspr r3, HID0
isync
rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */
sync
isync
mtspr HID0, r4 /* HID0 = r4 */
isync
/* Get cpu type */
mfspr r28, PVR
rlwinm r28, r28, 16, 16, 31
/* invalidate the MPU's data/instruction caches */
lis r3, 0x0
cmpli 0, 0, r28, CPU_TYPE_750
beq cpuIs750
cmpli 0, 0, r28, CPU_TYPE_7400
beq cpuIs750
cmpli 0, 0, r28, CPU_TYPE_7410
beq cpuIs7410
cmpli 0, 0, r28, CPU_TYPE_7450
beq cpuIs7450
cmpli 0, 0, r28, CPU_TYPE_7455
beq cpuIs7450
cmpli 0, 0, r28, CPU_TYPE_603
beq cpuIs603
cmpli 0, 0, r28, CPU_TYPE_603E
beq cpuIs603
cmpli 0, 0, r28, CPU_TYPE_603P
beq cpuIs603
cmpli 0, 0, r28, CPU_TYPE_604R
bne cpuNot604R
/* CPU is 604R */
isync /* isync before changing cache enables */
mtspr HID0, r3 /* disable the caches */
isync
ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */
cpuNot604R:
/* Unrecognized CPU types jump here, and 604R falls in */
ori r3, r3, (_PPC_HID0_ICFI | _PPC_HID0_DCFI)
cpuIs603:
/* 603, 603E, 603P jump here; 604R and unrecognized fall in */
ori r3, r3, (_PPC_HID0_ICE | _PPC_HID0_DCE)
or r4, r4, r3 /* set bits */
sync
isync
mtspr HID0, r4 /* HID0 = r4 */
isync
andc r4, r4, r3 /* clear bits */
cmpli 0, 0, r28, CPU_TYPE_604
beq cpuIs604
cmpli 0, 0, r28, CPU_TYPE_604E
beq cpuIs604
cmpli 0, 0, r28, CPU_TYPE_604R
beq cpuIs604
/* Following can't happen -- 750, 7400, 7410 are found earlier
* cmpli 0, 0, r28, CPU_TYPE_750
* beq cpuIs604
* cmpli 0, 0, r28, CPU_TYPE_7400
* beq cpuIs604
* cmpli 0, 0, r28, CPU_TYPE_7410
* beq cpuIs604
*/
/* 603, 603E, 603P, unrecognized */
isync
mtspr HID0, r4
isync
#ifdef USER_I_CACHE_ENABLE
b iCacheOn603
#else
b cacheEnableDone
#endif
cpuIs7410:
andi. r3, r3, 0
mtspr 1016,r3 /* 7410 bug, L2PMCR not cleared on reset */
b cpuIs750
cpuIs7450:
mfspr r3, HID0
sync
oris r3,r3,0x0400 # Set TBEN
oris r3,r3,0x0010 # Set DPM
mtspr HID0, r3
sync
b cpuIs750
cpuIs750:
/* Also handles 7400 and 7410 */
#ifdef USER_I_CACHE_ENABLE
mfspr r3,HID0
addis r4,r0,0x0000 /* Clear r4 */
ori r4,r4,0x8800 /* Setup bit pattern for ICE/ICFI */
or r3,r4,r3
isync
mtspr HID0,r3 /* set ICE/ICFI */
isync
addis r4,r0,0x0000 /* Clear r4 */
ori r4,r4,0x0800 /* Setup bit pattern for ICFI */
andc r3,r3,r4
isync
mtspr HID0,r3 /* clear IFCI (bit 16) */
isync
addis r4,r0,0x0000 /* Clear r4 */
ori r4,r4,0x2000 /* Setup bit pattern for ILOCK */
andc r3,r3,r4
isync
mtspr HID0,r3 /* clear ILOCK (bit 18) */
isync
sync
#endif
b cacheEnableDone
cpuIs604:
/* 604, 604E, 604R, only */
/* Enables and invalidates have been set in HID0,
* and the corresponding bits are cleared in r4.
* Loop count not increased for 7400, since it doesn't come here.
*/
lis r5, 0x0
ori r5, r5, 0x1000
mtspr CTR, r5
loopDelay:
nop
bdnz loopDelay
isync
mtspr HID0, r4
isync
/* turn the Instruction cache ON */
#ifdef USER_I_CACHE_ENABLE
ori r4, r4, (_PPC_HID0_ICE | _PPC_HID0_ICFI)
isync /* Synchronize for ICE enable */
mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
isync
b cacheEnableDone
iCacheOn603:
/* 603, 603E, 603P, unrecognized */
ori r4, r4, (_PPC_HID0_ICE | _PPC_HID0_ICFI)
rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
/*
* The setting of the instruction cache enable (ICE) bit must be
* preceded by an isync instruction to prevent the cache from being
* enabled or disabled while an instruction access is in progress.
*/
isync
mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
mtspr HID0, r3 /* using 2 consec instructions */
/* PPC603 recommendation */
isync
#endif
cacheEnableDone:
/* All processor types end up here */
/* disable instruction and data translations in the MMU */
sync
mfmsr r3 /* get the value in msr *
/* clear bits IR and DR */
rlwinm r4, r3, 0, _PPC_MSR_BIT_DR+1, _PPC_MSR_BIT_IR - 1
mtmsr r4 /* set the msr */
isync
sync /* SYNC */
/* initialize the BAT register */
li p3,0 /* clear p0 */
isync
mtspr IBAT0U,p3 /* SPR 528 (IBAT0U) */
isync
mtspr IBAT0L,p3 /* SPR 529 (IBAT0L) */
isync
mtspr IBAT1U,p3 /* SPR 530 (IBAT1U) */
isync
mtspr IBAT1L,p3 /* SPR 531 (IBAT1L) */
isync
mtspr IBAT2U,p3 /* SPR 532 (IBAT2U) */
isync
mtspr IBAT2L,p3 /* SPR 533 (IBAT2L) */
isync
mtspr IBAT3U,p3 /* SPR 534 (IBAT3U) */
isync
mtspr IBAT3L,p3 /* SPR 535 (IBAT3L) */
isync
mtspr DBAT0U,p3 /* SPR 536 (DBAT0U) */
isync
mtspr DBAT0L,p3 /* SPR 537 (DBAT0L) */
isync
mtspr DBAT1U,p3 /* SPR 538 (DBAT1U) */
isync
mtspr DBAT1L,p3 /* SPR 539 (DBAT1L) */
isync
mtspr DBAT2U,p3 /* SPR 540 (DBAT2U) */
isync
mtspr DBAT2L,p3 /* SPR 541 (DBAT2L) */
isync
mtspr DBAT3U,p3 /* SPR 542 (DBAT3U) */
isync
mtspr DBAT3L,p3 /* SPR 543 (DBAT3L) */
isync
/* invalidate entries within both TLBs */
li p1,128
xor p0,p0,p0 /* p0 = 0 */
mtctr p1 /* CTR = 32 */
isync /* context sync req'd before tlbie */
sysALoop:
tlbie p0
addi p0,p0,0x1000 /* increment bits 15-19 */
bdnz sysALoop /* decrement CTR, branch if CTR != 0 */
sync /* sync instr req'd after tlbie */
/* initialize Small Data Area (SDA) start address */
#if FALSE /* XXX TPR NO SDA for now */
lis r2, HI(_SDA2_BASE_)
addi r2, r2, LO(_SDA2_BASE_)
lis r13, HI(_SDA_BASE_)
addi r13, r13, LO(_SDA_BASE_)
#endif
#if 0
LOOP:
/**************循环1************/
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