config.h

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#define ROM_BASE_ADRS           0xfff00000      /* base address of ROM */
#define ROM_TEXT_ADRS           (ROM_BASE_ADRS+0x0100) /* with PC & SP */
#define ROM_WARM_ADRS           (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */
#define ROM_SIZE                0x00080000      /* 512KB ROM space */
#define RAM_LOW_ADRS            0x00100000/*0x00010000*/   /* RAM address for vxWorks */
#define RAM_HIGH_ADRS           0x00f00000   /* RAM address for bootrom */

/* memory configuration */

#define LOCAL_MEM_LOCAL_ADRS    0x0
#define LOCAL_MEM_SIZE          0x04000000      /* 128 M */

#define USER_RESERVED_MEM       0x0

#undef  LOCAL_MEM_AUTOSIZE                      /* run-time memory sizing */

#define SYS_CLK_RATE		100/* default system clock rate */


/* Serial port configuration */

#ifdef INCLUDE_DUART
#   define NUM_DUART_TTY    1/*2*/
#else
#   define NUM_DUART_TTY    0
#endif /* INCLUDE_DUART */

#undef  NUM_TTY
#define NUM_TTY        N_SIO_CHANNELS+NUM_DUART_TTY  /* sio channel defined in sp.h */

#undef  WDB_COMM_TYPE 
#define WDB_COMM_TYPE  WDB_COMM_SERIAL /* communication through serial port */


#undef CONSOLE_TTY
#define CONSOLE_TTY  0 /*DUART1*/


#if 0
#define INCLUDE_PC_CONSOLE            /* PC keyboard and VGA console */
#endif

#ifdef INCLUDE_PC_CONSOLE
#define PC_CONSOLE           (0)      /* console number */
#define N_VIRTUAL_CONSOLES   (2)      /* shell / application */
#endif /* INCLUDE_PC_CONSOLE 

/* PS/2 101-key default keyboard type (use PC_XT_83_KBD for 83-key) */

#define PC_KBD_TYPE   (PC_PS2_101_KBD)


/*
#undef  WDB_TTY_BAUD
#define WDB_TTY_BAUD    38400
*/
/*
 * Cache configuration
 *
 * Note that when MMU is enabled, cache modes are controlled by
 * the MMU table entries in sysPhysMemDesc[], not the cache mode
 * macros defined here.
 */

/* instruction cache */

#define	USER_I_CACHE_ENABLE		/* Enable INSTRUCTION CACHE */
#undef	USER_I_CACHE_MODE
#define USER_I_CACHE_MODE CACHE_COPYBACK /* select COPYBACK or WRITETHROUGH */

/* data cache */

#define  USER_D_CACHE_ENABLE		 /* Enable DATA CACHE */
#undef  USER_D_CACHE_MODE
#define USER_D_CACHE_MODE CACHE_COPYBACK  /* select COPYBACK or DISABLED */

/*
 * L2 Cache
 *
 * Note that L2 cache is not supported by all PPC CPUs. L2 cache is supported
 * on 750, 755, 7400, 7410, but not on sp8240.
 */

#if (defined(SP8240) || defined(SP745))
#undef  INCLUDE_CACHE_L2          /* No L2 support on 8240,745 */
#endif

/*
 * L2 Private Memory (L2PM) Support:
 *
 * Note: Not all PPC CPUs support L2PM, and currently only 755 and 7410
 * support this feature.  
 * Note * INCLUDE_L2PM should not be defined for a 7400 CPU, so -DSP7410
 *        is needed.
 *      * INCLUDE_CACHE_L2 had to included if L2 Private Memory is desired.
 */

#if !(defined(SP755) || defined(SP7410))
#undef	INCLUDE_L2PM    
#endif /* SP755 || SP7410 */

#ifdef INCLUDE_CACHE_L2

#define L2CACHE_MODE_WRITETHROUGH	0
#define L2CACHE_MODE_COPYBACK	        1
   
/* Set the default L2 cache mode */

#define L2CACHE_MODE	    L2CACHE_MODE_COPYBACK

    
#ifdef  INCLUDE_CACHE_L2
#define L2_CACHE_SIZE	    L2CR_SIZE_1MB      /* 1MB  in sysL2BackCache.h */
#endif  /* INCLUDE_CACHE_L2 */

#ifdef INCLUDE_L2PM

/*
 * Base Address for L2 SRAM being used as private memory.
 *
 * Local RAM size is configured as 16M, and base address for private memory
 * for L2 SRAM is configured where the local RAM ends. Make sure that the
 * L2 SRAM area does not overlap with existing RAM or IO area.
 */

#define L2PM_SRAM_ADRS          0x010000000 /* to match with LOCAL_MEM_SIZE */

/*
 * L2 SRAM Private Memory Configuration:
 *
 * The PPMC755 or PPMC7410 Altimus board supports 1MB of L2 SRAM, and
 * the BSP configures this memory as 512K for L2 Cache and 512K for
 * private memory.
 *
 * The table below shows the different configurations in which L2 SRAM can be
 * used.
 *
 * Configured only  | Configured as L2 Cache | Configured only as 
 * as L2 Cache      | and Private Memory     | Private Memory
 *------------------------------------------------------------------------
 * L2E     = 1      | L2E      = 1           | L2E      = 0      
 * L2SIZE  = 11(1MB)| L2SIZE   = 10 (512KB)  | L2Size   = don't care
 * L2PMSIZE= 00     | L2PMSIZE = 10 (512KB)  | L2PMSIZE = 11 (1MB)
 *        (disabled)|                        |
 *                  |                        |
 */
    
/* L2PM config bits to determine the size of private memory
 * Define INCLUDE_CACHE_L2 with L2_CACHE_SIZE = 0 means L2CR_SIZE_2MB
 * Undef INCLUDE_CACHE_L2 for no L2 cache
 */
#define L2PM_SIZE               L2PM_SIZE_512KB
#ifdef INCLUDE_CACHE_L2
#   undef  L2_CACHE_SIZE
#   define L2_CACHE_SIZE        L2CR_SIZE_512KB
#else
#   define L2_CACHE_SIZE        0
#endif  /* INCLUDE_CACHE_L2 */

#if (L2PM_SIZE == L2PM_SIZE_2M)
#   define L2PM_PHYMEM_SIZE     0x200000
#elif (L2PM_SIZE == L2PM_SIZE_1M)
#   define L2PM_PHYMEM_SIZE     0x100000
#elif (L2PM_SIZE == L2PM_SIZE_512KB)
#   define L2PM_PHYMEM_SIZE     0x80000
#else /* less than 256KB not allowed */
#   define L2PM_PHYMEM_SIZE     0x40000
#endif /* L2PM_SIZE */

#endif /* INCLUDE_L2PM*/

#endif /* INCLUDE_CACHE_L2  */

/* This value MUST match the Sandpoint system 60x bus speed */

#ifdef SP8240
#define DEC_CLOCK_FREQ          66666666        /* 66MHz default */
#else
#define DEC_CLOCK_FREQ          100000000       /* 100MHz default */
#endif

#define DEC_CLOCK_FREQ          100000000       /* 100MHz default */

#define INCLUDE_WINDML

#ifdef  INCLUDE_WINDML
#ifndef INCLUDE_PCI
#define INCLUDE_PCI
#endif
#undef INCLUDE_WINDML_PS2_KEYBOARD
#undef INCLUDE_WINDML_PS2_POINTER
#define INCLUDE_WINDML_USB_KEYBOARD
#define INCLUDE_WINDML_USB_POINTER
#define INCLUDE_PCI_WINDML_GRAPHICS
#define INCLUDE_UGL_ALL
#endif /* INCLUDE_WINDML */

/* Network driver configuration */

#ifdef INCLUDE_NETWORK

/* define to use END drivers, undef to use netif drivers */

#define INCLUDE_END
    
#ifndef INCLUDE_END	/* not using SENS, use netif driver */

#undef  WDB_COMM_TYPE  		/* WDB agent comm. */
#define WDB_COMM_TYPE		WDB_COMM_NETWORK

/*
 * The following NETIF... macros augment the NETIF table defined in
 * "usrNetwork.c".  The NETIF table entry defined here will be compiled
 * at the beginning of the table and thus be found first prior to the
 * "dcattach()" call.  Instead of calling "dcattach()" directly, the
 * function "sysDynDcAttach()" is called which in turn calls "dcattach()"
 * with a DYNAMICALLY determined CPU based I/O address, rather than
 * the statically compiled address IO_ADRS_DC.
 */
#define INCLUDE_DC_NETIF
#define NETIF_USR_DECL  IMPORT STATUS sysDynDcAttach(); 	\
                    IMPORT STATUS dcattach();

#define NETIF_USR_ENTRIES \
 		{ "dc", sysDynDcAttach, (char*)IO_ADRS_DC, 	\
		  INT_VEC_DC, INT_LVL_DC, DC_POOL_ADRS, 	\
		  DC_POOL_SIZE, DC_DATA_WIDTH, DC_RAM_PCI_ADRS, DC_MODE },

#endif /* ifndef INCLUDE_END */

#ifdef INCLUDE_END			/* We are using END/SENS */

#undef  WDB_COMM_TYPE  		/* make WDB agent comm. path a END device */
#define WDB_COMM_TYPE		WDB_COMM_END    
    
/*
 * For one END network device:
 *
 * #define INCLUDE_PRIMARY_END
 * Set the PRIMARY_ENDTYPE to one of the supported types.
 *
 * Current supported types are:
 *
 * DEC_END_DEVICE    1 - dc    dec21x40End driver
 * FEI_END_DEVICE    2 - fei   fei82557End driver
 * AMD_END_DEVICE    3 - lnPci AMD 79C97x End driver
 * ELPCI_END_DEVICE  4 - elPci 3COM 3c90x End driver
 * 
 * Secondary devices are not currently supported.
 *
 */

#ifdef  INCLUDE_PRIMARY_END

#if FALSE    
#define PRIMARY_ENDTYPE         DEC_END_DEVICE        
#define PRIMARY_ENDTYPE         FEI_END_DEVICE        
#define PRIMARY_ENDTYPE         AMD_END_DEVICE        
#define PRIMARY_ENDTYPE         ELPCI_END_DEVICE        
#endif

#define PRIMARY_ENDTYPE         FEI_END_DEVICE        
#endif /* INCLUDE_PRIMARY_END */

#endif  /* INCLUDE_END */
#endif	/* INCLUDE_NETWORK */


/* ATA disk configuration */

#ifdef  INCLUDE_ATA_686

/*
 * The ATA_DEVx_STATE determines whether the ATA driver should probe
 * for a device.  
 *
 *      ATA_DEV_PRESENT		 = probe for the device; 
 *      ATA_DEV_NOT_PRESENT	 = don't probe for the device.
 *
 * To probe for all devices connect to both buses,
 * change all ATA_DEVx_STATE values to DEV_PRESENT.
 *
 *	ATA_DEV0_STATE = cntlr 0 / device 0
 *	ATA_DEV1_STATE = cntlr 0 / device 1
 *	ATA_DEV2_STATE = cntlr 1 / device 0
 *	ATA_DEV3_STATE = cntlr 1 / device 1
 */

#define	ATA_DEV0_STATE	ATA_DEV_PRESENT
#define	ATA_DEV1_STATE	ATA_DEV_PRESENT
#define	ATA_DEV2_STATE	ATA_DEV_PRESENT
#define	ATA_DEV3_STATE	ATA_DEV_PRESENT

#ifndef	INCLUDE_DOSFS
#define	INCLUDE_DOSFS		/* file system to be used */
#endif	/* INCLUDE_DOSFS */

#endif	/* INCLUDE_ATA_686 */

/*
 * User application initialization
 *
 * USER_APPL_INIT must be a valid C statement or block.  It is
 * included in the usrRoot() routine only if INCLUDE_USER_APPL is
 * defined.  The code for USER_APPL_INIT is only an example.  The
 * user is expected to change it as needed.  The use of taskSpawn
 * is recommended over direct execution of the user routine.
 */

#define	USER_APPL_INIT \
	{ \
	IMPORT int myAppInit(); \
	taskSpawn ("myApp", 30, 0, 5120, \
		   mpAppInit, 0x1, 0x2, 0x3, 0,0,0,0,0,0,0); \
	}

#include "sp.h"           /* Verify user options, specify i/o addr etc */

#ifdef __cplusplus
}
#endif

#endif  /* INCconfigh */

#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif