target.nr

cpc-1631的BSP包for VxWorks操作系统

ROM.

.SH "SPECIAL CONSIDERATIONS"

The Sandpoint hardware does not include an onboard ethernet
controller. The user will need to supply a PCI ethernet controller
card. The supported ethernet chip types include:

.TS E
expand,tab(|);
lf3 lf3 lf3 lf3 lf3
l l l l l .
.sp .5 
Device | Vendor | Bus | NETIF | SENS/END
_
21040 | Digital | PCI | yes | yes
21140 | Digital | PCI | yes | yes
21143 | Digital | PCI | no  | yes
82557 | Intel | PCI | no | yes 
82558 | Intel | PCI | no | yes 
82559 | Intel | PCI | no | yes 
79C970 | AMD | PCI | no | yes
79C971 | AMD | PCI | no | yes
79C972 | AMD | PCI | no | yes

3c90X  |3Com | PCI | no | yes
.TE


.IP
D-Link DFE-500Tx - Rev C6 (DEC 21140)  (both netif and END drivers)
.IP
D-Link DFE-500Tx - Rev C2 (DEC 21140)  (both netif and END drivers)
.IP
DEC EB143 - PCI Rev 2.0   (DEC 21143)  (END driver only) 
.IP
Intel EtherExpress Pro100B PCI (82557 based) (END driver only)
.IP
Intel EtherExpress Pro100+ PCI (82558 based) (END driver only)
.IP
Intel EtherExpress Pro100+ PCI (82559 based) (END driver only)
.IP
AMD PcNet-FAST Level One (AMC972 based) (END only)
.IP
AMP RayLan 1001a PcNet-FAST (AMC972 based) (END only)
.LP 
          
.SS "Delivered Objects"
Delivered Objects in this version is
.CS
         ataDrv.o            - ATA/EIDE HDD driver
         ataShow.o           - ATA/EIDE HDD display
         if_dc.o             - DEC 21x4x Ethernet LAN network interface driver
         dec21x40End.o       - DEC 21x4x Ethernet LAN END driver
         fei82557End.o       - Intel 82557, 82558, 82559 END driver
         ln97xEnd.o          - AMD 79c97x END driver
         El3c90xEnd.o        - 3Com EtherLink 3C90x END driver
.CE

.SS "Support for L1 Cache Locking"
L1 cache locking is available for MPC8240, MPC750, MPC755, MPC7400 and
MPC7410. The cache lock routine can be used to lock the entire data
or instruction cache with a specified memory region. 

.SS "Support for L2 Cache"
L2 Cache is available for MPC750, MPC755, MPC7400,
MPC7410, MPC7450, MPC7455 & MPC7441. 
Callback function pointers for L2 cache Global Invalidation, L2 Cache Enable,
L2 Cache Flush and L2 Cache Disable are intialized in sysHwInit().
Note: The L2 Cache was not behaving consistently on the MPMCGYRUS Rev X2
      board on which the sp7445 bsp was tested. So  the L2 cache has to 
      disabled for the sp7445 BSP by undefing  INCLUDE_CACHE_L2 untill 
      the issue is resolved.

.SS "Support for L2 Private Memory"
This feature is supported only on PPMC755 or PPMC7410. Part of the L2
SRAM can be configured as private SRAM, and can be mapped to physical
address space. By default, INCLUDE_L2PM is defined for the sp755 BSP
which installs 512K of L2 cache SRAM as a private L2 SRAM region beyond
the local RAM region.  Since the PPMC7400 and PPMC7410 shares the same
BSP sp74xx, to enable L2PM support for the 7410, you need to use
-DSP7410 in the Makefile.  This can be done by commenting and
uncommenting the EXTRA_DEFINE lines in the Makefile.  

.SS "Support for L2 Cache Locking"
L2 cache locking is supported on MPC750, MPC755, MPC7400 and MPC7410. On these
CPUs L2 is implemented as an unified cache. The L2 cache lock library
can be used to lock data or instructions in the L2 cache.

.SS "Support for AltiVec"
MPC7400, MPC7410, MPC7450, MPC7455, MPC7441, MPC7445
support an altiVec sub-system
that implements vector processing. Support for altiVec is now available, but an
altiVec aware compiler must be used to create applications that
use altiVec instructions. The altiVec support, can be enabled by
defining INCLUDE_ALTIVEC in config.h

.SS "Support for cache snooping"
Note: Cache snooping is not supported in the present release.

It can be enabled by defining
SNOOP_ENABLE in config.h. When enabled, memory allocated via
cacheDmaAlloc will have both snoop enable MMU flag, and cache flag
turned on.  This is not recommended for this release.

.SS "Support for L3 Cache "
L3 cache is supported on MPC7450/MPC7455. The L3 Cache is implemented as a 
unified cache.


.SS "Make Targets"
The Release Macro in the Makefile is defined as

RELEASE		= bootrom.hex vxWorks vxWorks.st 

The following images can not be built.

.IP
vxWorks_rom ....................... image too big
.IP
vxWorks.res_rom .................. undefined reference to 'RAM_DST_ADRS'
.IP
vxWorks.res_rom_res_low .... image too big
.IP
bootrom_res .......................... undefined reference to 'RAM_DST_ADRS'
.LP

.SS "Note:" 
The ROM resident images have not been tested.

.SS "Known Problems"

PROBLEM #1:

Reading Device and Vendor Ids from PCI IDSEL 12 may cause the system
to hang. A workaround solution is to skip this IDSEL when reading PCI
devices. Example:

	for (idsel = 0; idsel < 32; idsel++)
	   if (idsel == 12) 
	      continue;
	   else
	     {
		.......
	     }

Switch S6 in shared slot 2 position does not appear to work if switches
S3 & S4 are placed in MODE 0.

Slot numbers are incorrectly labelled in the documentation.  The slot
numbers from the PPMC outward are 2,1,4,3 respectively.

PROBLEM #2 (IDE-Reset):

When ATA device is used, the warm reset appears to hang the board, and
the board has to be power-cycled.

PROBLEM #3 (ISA-DMA):

In the users manual revision 1.01, dated 6/9/1999, Board revision
Level X2, Errata Revision Level B, shows that "The Winbond PCIRST
signal conflicts with the PCIRST signal from the reset controller";
the reason being 'ISA-DMA does not seem to work'. This problem will
be fixed X3 revision of the board.

PROBLEM #4 (L2 CACHE):
 
In the PowerPC Evaluation System Users Manual Rev 4.01 dated 05/19/00,
Board revision Level X2, Altimus Errata Revision Level A, says that 
Problem: "If MPC750/MPC755 CPU's are installed and MCM69p737 SRAM's are
installed, pin B6(SE3) is undriven"
"If MPC7400 CPU's is used, or if  MCM69p737 SRAM's are used, then
pin B6 is either driven (address A17) or is ignored by SRAM" 
Impact:  "L2 cache may not operate or may not be reliable"
Work-Around: "Add a pulldown to LA17" OR "Use late-write devices (69R737)
that ignore pin B6(SE3)           "

PROBLEM #5 (L3 CACHE on PPMC7450):
 
The Product page on the Motorola web site and the Valis documentation
states that 2 MB of L3 cache is present. Actually only 1 MB of L3 Cache
is present.

Impact:  "If the L3 Cache is initialized with the L3 Cache size set to
2 MB, the system crashes."
Work-Around: "Make sure that the L3 Cache Size is set to 1 MB when
initializing the L3 Cache."

.SS "Processor Card DIP Switch Settings

.TS E
expand,tab(|);
lf3 lf3 lf3 lf3 
l l l l  .
.sp .4 
SW1 | PPMC-7400 X2 / PPMC-750 / PPMC-755 / PPMC-7400 X3 / PPMC-7410 X3
_
1 | ON
2 | ON
3 | ON
4 | OFF
5 | ON
6 | ON
7 | ON
8 | OFF

MPC75x/74xx PLL : 4X 133  266  333  400
MPC107      PLL : PCI=33 , BUS = 100

SW1 | PPMC-7450 X1 | PPMC7450 X2
    Refer to the Sandpoint X3 Valis Documentation.


MPC7450 (PPMC7450-X1) PLL : 6X 400  500  600  800
MPC107     PLL : PCI=33 , BUS = 100
 
MPC7450 (PPMC7450-X2) PLL : 8X 533  666  800 
MPC107     PLL : PCI=33 , BUS = 100

MPC744x    PLL : 6X  400 500 600 800
MPC107     PLL : PCI=33 , BUS = 100

SW1/SW2  PPMC-7455 X1/X2 
    Refer to the Sandpoint 111 Documentation.

Note: As of this beta release for Tornado 2.2 the documentation is
      not available for the Switch settings. The BSP was tested with
      the settings that came preset.
      Update this section before RTM.

SW1: 1   2   3   4  5  6  7  8
     ON OFF OFF ON ON ON ON OFF

SW2: 1   2   3   4  5  6  7  8
     ON OFF ON OFF ON ON OFF OFF
.TE

.TS E
expand,tab(|);
lf3 lf3 lf3 lf3 
l l l l  .
.sp .4 
SW2 : PPMC-7400 X2 / PPMC-755 / PPMC750
=======================================
SYSRST   : COP Resets only PrMC
PCI66MHZ : 33 MHz Only
TRIGSEL  : Trigger In
PROGSEL  : RCS1 on Local ROM 
AGENT    : Free Agent
PrMCTYPE : MOTSPS PrPMC
MAPSEL   : Map B / CHRP
ROMLOC   : RCS0 on PCI


SW2 : PPMC-7400 X3 / PPMC-7410 X3 / PPMC-7450 X1/X2 / PPMC-744x X2
=============================
SYSRST   : COP Resets only PrMC
M66EN    : 33 MHz Only
ROMSEL   : Standard Flash Selected
PROGSEL  : Local Flash is Bootable
AGENT    : Free Agent
PMCTYPE  : MOTSPS PrPMC
MAPSEL   : Map B / CHRP
ROMLOC   : RCS0 on PCI
.TE

.SH "X2 BASEBOARD LAYOUT"

The diagram below shows jumpers relevant to VxWorks configuration.


.bS

                                        C                     C 
                                        O                     O  
                                        M   PARA  MOU   KEY   M  
                                        2   LLEL   SE   BORD  1  
 _____________________________________________________________________
|              ________               |   ||     ||   ||   ||   |     |
|           s3|.____||_|              |___||_____||___||___||___|     |
|              ________                                               |
|           s4|_||____.|                                              |
|                                       ___________________________   |
|            _  _  _  _                 |                          |  |
|           |p||p||p||p|                |                          |  |
|           |c||c||c||c|                |                          |  |
|   ______  |i||i||i||i|                |         P P M C          |  |
|s6|.__||_| |s||s|| || |                |                          |  |
|           |l||l||s||s|                |      8240 or 755 or 750  |  |
|           |o||o||l||l|                |      7400 or 7410        |  |
|           |t||t||o||o|                |                          |  |
|           |3||4||t||t|                |                          |  |
|           |_||_|| || |                |__________________________|  |
|                 |1||2|                                        ___   |
|                 | || |                                J J J  | | |  |
|                 | || |                      ____      3 3 3  | | |  |
|1 _ 2      ____  | || |                     | U6 |     0 2 1  | | |  |   
| | |    s5|___.| |_||_|                     | ROM|            |_|_|  |
| | |                                        |____|              __   |
| | |M   R   P                                                  |  |  |
| | |I   E   O                                                  |  |  |
| | |S   S   W                                                  |  |  |
| | |C   E   E                 _  _      _________              |  |  |
| | |   _T   R_               |J||J|    |IDE 2    |             |  |  |
| | |  |s2| |s1|              |3||3|    |_________|             |__|  |
| |_|  |__| |__|              |3||4|    __________    __________      |
|                 ____B____   |_||_|   |IDE 1     |  |FLOPPY    |     |
|                |_________|          1|__________| 1|__________|     |
|_____________________________________________________________________|


   S3, S4 Mode Switches      PPMC- Processor card
   B-  Battery Connector     Symbols (||) in Switches indicates default mode
   U6- Rom Socket             

.bE

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration," 
.pG "Architecture Appendix"

.SH "SUPPORT INFORMATION"

.CS
telephone: [phone]   
email:     [e-mail]   
fax:       [phone]
.CE

.SH "BIBLIOGRAPHY"
.iB "Sandpoint User's Manual and Hardware Design Manual"
.iB "http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html"
.iB "MPC8240 Integrated Processor User's Manual"
.iB "MPC755 Processor User Manual"
.iB "MPC750 Processor User Manual"
.iB "MPC7400 Processor User Manual"
.iB "MPC7410 Processor User Manual"
.iB "SPS BSP user manual
.iB "MPC107 PCI Bridge/Memory Controller User's Manual"
.iB "Addendum to MPC107 PCI Bridge/Memory Controller User苨 Manual"
.iB "MPC107 Revision 4.0 Supplement and User's Manual Errata"
.iB "Winbond W83C553F SYSTEM I/O CONTROLLER WITH PCI ARBITER User Manual"
.iB "National Semiconductor PC87308VUL SuperIO User's Manual"
.iB "DEC 2114X Ethernet Controller User's Manual"
.iB "Intel 82557 Ethernet Controller User's Manual"
.iB "AMD 97X PCFAST Ethernet Controller User's Manual"
.iB "Am29F040B 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, "
.iB "Uniform Sector Flash Memory Manual."
.iB "PCI Local Bus Specification Revision 2.1"
.iB "PowerPC Embedded Application Binary Interface 32-Bit Implementation"
.iB "Altimus X2 Release V1.1 Schematics"