pci.h

cpc-1631的BSP包for VxWorks操作系统

#define	PCI_MM_AUDIO		0x1   /* Audio device */
#define	PCI_MM_OTHER		0x80  /* Other Multimedia Device */

/*
 * PCI Sub-class codes - base class 0x5
 */
#define	PCI_MEM_RAM		0x0   /* RAM device */
#define	PCI_MEM_FLASH		0x1   /* FLASH device */
#define	PCI_MEM_OTHER		0x80  /* Other Memory Controller */

/*
 * PCI Sub-class codes - base class 0x6
 */
#define	PCI_BRIDGE_HOST		0x0   /* Host/PCI Bridge */
#define	PCI_BRIDGE_ISA		0x1   /* PCI/ISA Bridge */
#define	PCI_BRIDGE_EISA		0x2   /* PCI/EISA Bridge */
#define	PCI_BRIDGE_MC		0x3   /* PCI/MC Bridge */
#define	PCI_BRIDGE_PCI		0x4   /* PCI/PCI Bridge */
#define	PCI_BRIDGE_PCMCIA	0x5   /* PCI/PCMCIA Bridge */
#define	PCI_BRIDGE_NUBUS	0x6   /* PCI/NUBUS Bridge */
#define	PCI_BRIDGE_CARDBUS	0x7   /* PCI/CARDBUS Bridge */
#define	PCI_BRIDGE_OTHER	0x80  /* PCI/Other Bridge Device */

/*
 * PCI Sub-class codes - base class 0x7
 */
#define	PCI_COMM_GENERIC_XT	0x0   /* XT Compatible Serial Controller */
#define	PCI_COMM_PARALLEL	0x1   /* Parallel Port Controller */
#define	PCI_COMM_OTHER		0x80  /* Other Communications Controller */

/*
 * PCI Sub-class codes - base class 0x8
 */
#define	PCI_PERIPH_PIC		0x0   /* Generic PIC */
#define	PCI_PERIPH_DMA		0x1   /* Generic DMA Controller */
#define	PCI_PERIPH_TIMER	0x2   /* Generic System Timer Controller */
#define	PCI_PERIPH_RTC		0x3   /* Generic RTC Controller */
#define	PCI_PERIPH_OTHER	0x80  /* Other System Peripheral */

/*
 * PCI Sub-class codes - base class 0x9
 */
#define	PCI_INPUT_KEYBOARD	0x0   /* Keyboard Controler */
#define	PCI_INPUT_DIGITIZ	0x1   /* Digitizer (Pen) */
#define	PCI_INPUT_MOUSE		0x2   /* Mouse Controller */
#define	PCI_INPUT_OTHER		0x80  /* Other Input Controller */

/*
 * PCI Sub-class codes - base class 0xa
 */
#define	PCI_DOCK_GENERIC	0x0   /* Generic Docking Station */
#define	PCI_DOCK_OTHER		0x80  /* Other Type of Docking Station */

/*
 * PCI Sub-class codes - base class 0xb
 */
#define	PCI_PROCESSOR_386	0x0   /* 386 */
#define	PCI_PROCESSOR_486	0x1   /* 486 */
#define	PCI_PROCESSOR_PENT	0x2   /* Pentium */
#define	PCI_PROCESSOR_ALPHA	0x10  /* Alpha */
#define	PCI_PROCESSOR_COPROC	0x40  /* Co-processor */

/*
 * PCI Sub-class codes - base class 0xc
 */
#define	PCI_SERIAL_FIRE		0x0   /* FireWire (IEEE 1394) */
#define	PCI_SERIAL_ACCESS	0x1   /* ACCESS.bus */
#define	PCI_SERIAL_SSA		0x2   /* SSA */

/* PCI header decode */
#define	PCI_HEADER_MULTI	0x80  /* multi-function device */
#define	PCI_HEADER_ZERO		0x00  /* type zero PCI header */
#define	PCI_HEADER_ONE		0x01  /* type one PCI header */
#define	PCI_HEADER_PPB		PCI_HEADER_ONE	/* type one PCI to PCI Bridge */

#define	PCI_HEADER_TYPE_M	0x3f  /* type mask for header */

/*
 * Base register bit definitions.
 */
#define	PCI_BASE_SPACE_M    0x00000001	/* memory space indicator */
#define	PCI_BASE_SPACE_IO   0x1	  /* IO space */
#define	PCI_BASE_SPACE_MEM  0x0	  /* memory space */

#define	PCI_BASE_TYPE_MEM   0x0	  /* 32-bit memory address */
#define	PCI_BASE_TYPE_LOW   0x2	  /* less than 1Mb address */
#define	PCI_BASE_TYPE_ALL   0x4	  /* 64-bit memory address */
#define	PCI_BASE_TYPE_RES   0x6	  /* reserved */

#define	PCI_BASE_TYPE_M		0x00000006  /* type indicator mask */
#define	PCI_BASE_PREF_M		0x00000008  /* prefetch mask */
#define	PCI_BASE_M_ADDR_M	0xfffffff0  /* memory address mask */
#define	PCI_BASE_IO_ADDR_M	0xfffffffe  /* I/O address mask */

/*
 * other interesting PCI constants
 */
#define	PCI_BASE_NUM	6	/* num of base regs in configuration header */
#define	PCI_BASE_SIZE	4	/* size of base reg in bytes */
#define	PCI_CONF_HDR_SIZE	256	/* configuration header size */

#define	PCI_HARDDEC_8514 2	/* number of reg entries for 8514 hard-decode */
#define	PCI_HARDDEC_VGA	3	/* number of reg entries for VGA hard-decode */
#define	PCI_HARDDEC_IDE	4	/* number of reg entries for IDE hard-decode */
#define	PCI_HARDDEC_IDE_PRI 2	/* number of reg entries for IDE primary */
#define	PCI_HARDDEC_IDE_SEC 2	/* number of reg entries for IDE secondary */

/*
 * PCI to PCI bus bridge
 */
#define	PCI_PPB_ROM		0x38	/* expansion ROM base address */
#define	PCI_PPB_BASE_NUM	0x2	/* number of base registers */

#ifdef SANDPOINT
/* NOTE: Keep these in sync with config.h and sysLib.c in BSPs */
# define PCI_SOC_MBAR0		0x81000000
# define PCI_SOC_MBAR(unit)	(PCI_SOC_MBAR0 + (unit) * PCI_SOC_MEM_WINSZ)
#endif

#ifdef MOUSSE
/* NOTE: Keep these in sync with config.h and sysLib.c in BSPs */
# define PCI_SOC_MBAR0		0x81000000
# define PCI_SOC_MBAR(unit)	(PCI_SOC_MBAR0 + (unit) * PCI_SOC_MEM_WINSZ)
# define PCI_SOC_INTLINE(unit)	2		/* MOUSSE_IRQ_CPCI */
#endif

#ifdef JUPITER
# define PCI_SOC_INTLINE(unit)	0
#endif

#ifdef EVIL
# define PCI_SOC_MBAR0		0x03000000
# define PCI_SOC_MBAR(unit)	(PCI_SOC_MBAR0 + (unit) * PCI_SOC_MEM_WINSZ)
# define PCI_SOC_INTLINE(unit)	5
#endif


#ifdef PLISIM
# define PCI_SOC_MBAR(unit)	0xcd600000	/* Arbitrary value */
# define PCI_SOC_INTLINE(unit)	0
#endif /* PLISIM */

/*
 * PCI swapping for memory reads as well as DMA'd data is required on
 * big-endian hosts EXCEPT where the PCI bridge and/or PCI chip
 * perform the swapping automatically.  
 */

#if !defined(LE_HOST) && !defined(PLISIM)
# define PCI_SWAP_REQUIRED
#endif

/*
 * Define PCI_SWAP_INLINE only if your compiler supports inlining.
 * Otherwise, an regular function is defined in OSL/pci_common.c.
 */

#if defined(VXWORKS) && !defined(ANSI)
# define PCI_SWAP_INLINE
#endif

#ifdef PCI_SWAP_REQUIRED
#ifdef PCI_SWAP_INLINE
#if 0
UINT32 pci_swap(UINT32 val) {
	val = val << 16 | val >> 16;
	return (val & 0xff00ffff) >> 8 | (val & 0xffff00ff) << 8;
    }
#endif
# else /* !PCI_SWAP_INLINE */
    extern UINT32 pci_swap(UINT32 val);
# endif /* !PCI_SWAP_INLINE */
#else /* !PCI_SWAP_REQUIRED */
# define pci_swap(val)		(val)
#endif /* !PCI_SWAP_REQUIRED */

typedef void (*pci_isr_t)(void *isr_data);

typedef struct pci_dev_s {
    int		busNo;
    int		devNo;
    int		funcNo;
} pci_dev_t;

struct pci_device_id {
	unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
};

#define PCI_ANY_ID (~0)

int	pci_dma_putw(pci_dev_t *, UINT32 addr, UINT32 data);
int	pci_dma_puth(pci_dev_t *, UINT32 addr, UINT16 data);
int	pci_dma_putb(pci_dev_t *, UINT32 addr, UINT8 data);
UINT32	pci_dma_getw(pci_dev_t *, UINT32 addr);
UINT16	pci_dma_geth(pci_dev_t *, UINT32 addr);
UINT8	pci_dma_getb(pci_dev_t *, UINT32 addr);
int	pci_config_putw(pci_dev_t *, UINT32 addr, UINT32 data);
UINT32	pci_config_getw(pci_dev_t *, UINT32 addr);
int	pci_memory_putw(pci_dev_t *, UINT32 addr, UINT32 data);
UINT32	pci_memory_getw(pci_dev_t *, UINT32 addr);
void	pci_print_all(void);
void	pci_print_config(pci_dev_t *);
int	pci_find_device(int vendorID,
			int deviceID,
			int index,		/* Find the nth device */
			pci_dev_t *dev);
int	pci_int_connect(int intLine, pci_isr_t isr, void *isr_data);
int pci_configure_device(pci_dev_t* dev,
			 UINT32 io, UINT32 mem, UINT32 cmd);

/* Linux compatible API */
int pci_read_config_byte(pci_dev_t dev, int where, UINT8 *val);
int pci_read_config_word(pci_dev_t dev, int where, UINT16 *val);
int pci_read_config_dword(pci_dev_t dev, int where, UINT32 *val);
int pci_write_config_byte(pci_dev_t dev, int where, UINT8 val);
int pci_write_config_word(pci_dev_t dev, int where, UINT16 val);
int pci_write_config_dword(pci_dev_t dev, int where, UINT32 val);
pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);

/* Pull in device/vendor ID's */
#include "pci_ids.h"

#endif /* _OSL_PCI_H */