rominit111.s

cpc-1631的BSP包for VxWorks操作系统

	lis	r3,0x8000		/* Select CACHE_LINE_SIZE*/
	ori	r3,r3,0x000c
   	li      r4,0x08      		/* Set to 0x08 */

	stwbrx	r3,0,r5
	sync
	stb	r4,0(r6)
	sync         

    LOADPTR (r3, MPC107_PCICMD_ADRS)	/* program MPC107's PCI cmd reg. */
	stwbrx	r3, 0,r5 
	sync
    li      r4,0x0006      		/* Set to 06 (Memory Space)*/
	stwbrx	r3,0,r5
	sync
	sthbrx  r4,0,r6
	sync

    
	LOADPTR (r3, MPC107_PCISTAT_ADRS)	/* Program MPC107's PCI status reg. */
	stwbrx	r3,0,r5
	li      r3, 0x0002      /* Add offset -- this register is 2 bytes */
	lhbrx   r4, r3, r6          	
	sync
	ori     r4, r4, 0xffff     	/* Clear all bits */
	sthbrx  r4, r3, r6         
	sync
	lwbrx  r4,0,r6
	sync
	
/*QDIMCZH debug start*/
	LOADPTR (r3, 0x80000044)	/* Program MPC107's PCI control reg. */
	stwbrx	r3,0,r5
	xor     r4,r4,r4
	lis      r4,0x8000
	ori      r4,r4,0x0000
    stwbrx	r4,0,r6			
	sync
/*QDIMCZH debug end */	
      
	/* 
	 * SDRAM initialization code for the Sandpoint board
     */

	LOADPTR (r3, MPC107_PICR1_ADRS) /* Get PICR1 bits */
	stwbrx	r3,0,r5
    sync
	lwbrx	r4,0,r6			
	lis	r3, MPC107_PICR1_ROBITS_16
	ori	r3,r3, MPC107_PICR1_ROBITS_00
	and	r4,r4,r3	      /* preserve POR bits */


	lis     r3,0x0004      		/* processor type = 603/750*/

	ori     r3,r3,0x1000      	/* enable Flash write */
	ori     r3,r3,0x0800      	/* enable MCP* assertion*/
	ori     r3,r3,0x0200      	/* enable data bus parking */

/* The MPC8245, unlike the MPC840 or MPC107, reintroduces the idea 
 * of preventing mis-matched writes to ROM spaces.  Bit 7 disables
 * this feature, which we need for I/O and flash programming.
*/
  	ori     r3,r3,0x0100      	/* MPC8245: enable time base */
  	ori     r3,r3,0x0080      	/* MPC8245: disable write size checking*/

  	ori     r3,r3,0x0040      	/* enable PCI store gathering*/
	ori     r3,r3,0x0010      	/* LOOP_SNOOP -- must set:*/
	ori     r3,r3,0x0008      	/* enable address bus parking*/

	or      r4,r4,r3          	/* Set new config bits*/
	stwbrx  r4,0,r6
	sync

      
	LOADPTR (r3, MPC107_PICR2_ADRS)		
	stwbrx  r3,0,r5
	sync

	lis     r3,0x0000
	oris    r3,r3,0x0400      	/* FF0 is Local ROM*/


/* CF_KNA1 - set to 00 unless 1:1 or 3:2 CPU:BUS speeds (~150MHz core).*/
/* CF_KNA2 - set to 00 always */

	oris    r3,r3,0x0000      	// NORM: snoop wt states = 0

	stwbrx  r3,0,r6
    sync 

/* ===AMBOR=== Address Map B Options Register*/
/*
 *Even if Address Map B is not being used (though it should), the
 *memory DLL needs to be cleared/set/cleared before using memory.
 */

	LOADPTR (r3, 0x800000e0)		
    stwbrx 	r3,0,r5
    sync

	lwbrx	r4,0,r6			/* Get current bits */
	andi.	r4,r4,0xFFDF
    stwbrx	r4,0,r6			/* Clear DLL_RESET */
	sync
    ori	    r4,r4,0x0020
    stwbrx	r4,0,r6			/* Set DLL_RESET */
	sync
	andi.	r4,r4,0xFFDF
	
/*QDIMCZH debug start*/
	xor     r4,r4,r4
	lis      r4,0xc3b0
	ori      r4,r4,0x00c0
/*QDIMCZH debug end */	
    stwbrx	r4,0,r6			/* Clear DLL_RESET */
	sync
   
	LOADPTR (r3, MPC107_MCCR1_ADRS)
	stwbrx r3,0,r5
	sync

	lwbrx	r7,0,r6			/* Get MCCR1 bits; used w/MCCR4*/
	lis	r3,0x0040  
	and	r7,r7,r3		/* R7:  =0 if 32 bits, /= 0 if 64.*/
	
  	lis     r4,0x7580      		/* Safe Local ROM = 11+3 clocks*/


/*  Set all banks to same type (they don't have to be)*/

 	ori	r4,r4,0x0000		/* 64Mbit  4bank SDRAM*/

        stwbrx  r4,0,r6
        sync
	
	
	LOADPTR (r3, MPC107_MCCR2_ADRS)
	stwbrx r3,0,r5
	sync

	lis     r4,0x0000          	
	oris    r4,r4,0x0400      	/* ASRISE = 2 clocks*/
	oris    r4,r4,0x0040      	/* ASFALL = 2 clocks*/


/*
 * Select a refresh rate; it needs to match the bus speed; if too
 * slow, data may be lost; if too fast, performance is lost.  We
 * use the fastest value so we run at all speeds.
 * Refresh = (15600ns/busclk) - (213 (see UM)).
 */	
	ori     r4,r4,0x04cc      	/*  33 MHz mem bus (SAFE) =  307*/

	stwbrx  r4,0,r6
    sync
        
	LOADPTR (r3, MPC107_MCCR3_ADRS)
	stwbrx r3,0,r5
    sync

	lis     r4,0x7000          	/* BSTOPRE_M = 7 (see A/N) */
	oris    r4,r4,0x0800      	/* REFREC    = 8 clocks */

/*
 * RDLAT: Ignored on the MPC8245, almost always should be set to CL+1
 *        for the MPC8240.
 */

	oris    r4,r4,0x0040      	/* RDLAT     = 4 clocks (CL+1) SAFE*/

/*
 * The rest of the bits are EDO only; the MPMC824x does not support
 * EDO.
 */

	stwbrx  r4,0,r6
	sync       

	LOADPTR (r3, MPC107_MCCR4_ADRS)
	stwbrx r3,0,r5
	sync

	lis     r4,0x3000          	/* PRETOACT = 3 clocks*/
	oris    r4,r4,0x0500      	/* ACTOPRE  = 5 clocks*/
	oris    r4,r4,0x0010      	/* Registered buffers*/

	ori     r4,r4,0x3000      	/* CAS Latency (CL=3) (see RDLAT)*/
   	ori     r4,r4,0x0030      	/* ACTORW  = 3 clocks*/
   	ori     r4,r4,0x0009      	/* BSTOPRE_L = 9 (see A/N)*/

/*
 * Set the SDRAM size to 4- or 8-beat bursts for 64- or 32-bit bus mode,
 * respectively.
 */

    cmpwi	r7,0x0     		/* test 32/64 bit mode*/
    beq	k_is32bits
   	ori     r4,r4,0x0200      	/* Sequential wrap/4-beat burst*/
	b	mccr4set
k_is32bits:
   	ori     r4,r4,0x0300      	/* Sequential wrap/8-beat burst*/

mccr4set:
	stwbrx  r4,0,r6
	sync
	

/*
 * ===MSAR=== MEMORY START ADDRESS REGISTER
 *
 * MSAR1 / MSAR2 / MESAR1 / MESAR2
 *
 * All eight registers are programmed to non-overlapping values.
 * Assuming each bank controls 32Mb, the maximum address per bank
 * is 0x1FFFFFF; we set each bank to start at 0x0000000, 0x2000000, etc.
 * Since the lower "00000" are implied, we see the pattern 0x00, 0x20, in
 * the start registers (with the extended addresses all 0s).
 */     
       
	LOADPTR (r3, MPC107_MSAR1_ADRS)
	stwbrx r3,0,r5
	sync

	lis    r4,0x6040
	ori    r4,r4,0x2000
	stwbrx r4,0,r6
	

	LOADPTR (r3, MPC107_MSAR2_ADRS)
	stwbrx r3,0,r5
	sync

	lis    r4,0xe0c0
	ori    r4,r4,0xa080
	stwbrx r4,0,r6
	

	LOADPTR (r3, MPC107_XMSAR1_ADRS)
	stwbrx r3,0,r5
	sync

	lis    r4,0x0000
	ori    r4,r4,0x0000
	stwbrx r4,0,r6
	

	LOADPTR (r3, MPC107_XMSAR2_ADRS)
	stwbrx r3,0,r5
	sync

	lis    r4,0x0000
	ori    r4,r4,0x0000
	stwbrx r4,0,r6
	
/*
 * ===MEAR=== MEMORY END ADDRESS REGISTER
 *
 * MEAR1 / MEAR2 / MEEAR1 / MEEAR2
 * Similar to the previous values, less one from the next bank.
 * Therefore, 0x1F, 0x3F, etc.
 */

	LOADPTR (r3, MPC107_MEAR1_ADRS)
	stwbrx r3,0,r5
	sync

	lis    r4,0x7f5f
	ori    r4,r4,0x3f1f
	stwbrx r4,0,r6
	

	LOADPTR (r3, MPC107_MEAR2_ADRS)
	stwbrx r3,0,r5
	sync

    lis    r4,0xffdf
	ori    r4,r4,0xbf9f
	stwbrx r4,0,r6
	
	LOADPTR (r3, MPC107_XMEAR1_ADRS)
	stwbrx r3,0,r5
	sync

	lis    r4,0x0000
	ori    r4,r4,0x0000
	stwbrx r4,0,r6
	
	LOADPTR (r3, MPC107_XMEAR2_ADRS)
	stwbrx r3,0,r5
	sync

	lis    r4,0x0000
	ori    r4,r4,0x0000
	stwbrx r4,0,r6
	
 	LOADPTR (r3, MPC107_ODCR_ADRS)		/* Set ODCR */
	stwbrx r3,0,r5
	sync

   	lbz    r4, 3(r6)           	/* read current register state */
	li     r4, 0x00cd          	/* default setting */
	stb    r4, 3(r6)           	/* New settings. */

/*QDIMCZH debug start*/
	li     r4, 0x00          	/* default setting */
	stb    r4, 2(r6)           	/* New settings. */
/*QDIMCZH debug end */

	/* 
	 * The MPC106 Manual states M106_MBER_ADRS == M106_CFG_BASE + 0xa0, 
     * and that M106_MPMR_ADRS == M106_CFG_BASE + 0xa3. 
     * Interestingly, Both Dink32 and the MPC106 manual access both 
     * 8 bit (offset 0xa0 and 0xa3) registers in one 32bit operation, 
     * using stwbrx, which is questionable since they are eight bit 
     * registers.  It seems proper to access eight bit regiters with 
     * stbx, however to match the convention of Motorola Dink32 and 
     * the MPC106 manual code, both are written together with stwbrx.
	 */

	/* Enable memory banks and setup PAGE mode for SDRAM */

	LOADPTR (r3, MPC107_MBER_ADRS)
	stwbrx r3,0,r5
	sync

	li	r4,0x01		/* Enable bank 0 */
    stb  r4,0(r6)		
	
/*
 * ===PGMAX=== Page Max
 *
 * Refer to the MPC106 SDRAM programming A/N for details (applies to
 * MPC8240 also).
 */
 
   	lis    r3,0x80000000		
   	ori    r3,r3,0xa3
   	stwbrx r3,0,r5
   

    li     r4,0x0032                /*  33 MHz - w/ROMFAL=8 */

	stb    r4, 3(r6)           	/* Write PGMAX (note offset)*/

	/* Wait before initialize other registers */

	li	r4,0x3800
	mtctr   r4

PPMC8240wait200us:
	bdnz PPMC8240wait200us

	/* Set MEMGO bit */

	LOADPTR (r3, MPC107_MCCR1_ADRS)
	stwbrx r3,0,r5
	sync
	lwbrx  r4,0,r6			/* old MCCR1 */
	addis  r3,r0,0x0008
	ori    r3,r3,0x0000
	or     r4,r4,r3			/* set bits */
	stwbrx  r4,0,r6
	sync
	lwbrx  r4,0,r6			/* read in just to check */

	/* Wait again */

	li	r4, 8000
	mtctr	r4

PPMC8240wait8ref:

	bdnz	 PPMC8240wait8ref
	sync
	b	startCSetup	/* now do mmu setup for processor */

startCSetup:

/*QDIMCZH debug start*/
#define PUTC(ch)	li r3, ch; bl SEROUT

	PUTC(13)
	PUTC(10)
	PUTC(10)
	PUTC('B')
	PUTC('o')
	PUTC('o')
	PUTC('t')
	PUTC('i')
	PUTC('n')
	PUTC('g')
	PUTC('.')
	PUTC('.')
	PUTC('.')
	PUTC(13)
	PUTC(10)
	PUTC(10)
 /* QDIMCZH debug end */
 
#if	FALSE	/* EABI SDA not supported yet */

    /* initialize r2 and r13 according to EABI standard */

	LOADPTR (r2, _SDA2_BASE_)
	LOADPTR (r13, _SDA_BASE_)

#endif	/* FALSE */

	/* go to C entry point */

	or	r3, r11, r11		/* put startType in r3 (p0) */
	addi	sp, sp, -FRAMEBASESZ	/* save one frame stack */
#if 1
LOOP:
/**************循环1************/
	lis	r6, HIADJ(0x00100000)
	addi	r6, r6, LO(0x00100000 )
	
LOOPA:
	lis	r4, HIADJ(0xffc00002)	
	addi	r4, r4, LO(0xffc00002)

        /*****light LED*****/
        lis     r5,HIADJ(0xbf)/*任意值*/
        addi    r5,r5,LO(0xbf)
        stwbrx   r5,0,r4
        xor     r5,r5,r5

        addi    r6,r6,-1
        cmpwi   r6,0
        bne    LOOPA
/**************循环1************/     

/**************循环2************/
	lis	r6, HIADJ(0x00010000)
	addi	r6, r6, LO(0x00010000 )
	
LOOPB:
	lis	r4, HIADJ(0xffc00002)	
	addi	r4, r4, LO(0xffc00002)

        /*****Out LED*****/
        lis     r5,HIADJ(0xff)/*任意值*/
        addi    r5,r5,LO(0xff)
        stwbrx   r5,0,r4
        xor     r5,r5,r5

        addi    r6,r6,-1
        cmpwi   r6,0
        bne    LOOPB
/**************循环2************/     

    /*bl LOOP*/
#endif	
	LOADPTR (r6, romStart)
	LOADPTR (r7, romInit)
	LOADPTR (r8, ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8 

	mtlr	r6		/* romStart - romInit + ROM_TEXT_ADRS */
	blr

/*QDIMCZH debug start */
/**********************************************************************
 *  void SEROUT(int char);
 *
 *  Configure 8245-DUART to 9600 baud and write a character.
 *  Should be usable basically at any time.
 *
 *  r3 = character to output
 */

SEROUT:
	/* r4 = intLock() */
	mfmsr	r4
	rlwinm	r5,r4,0,17,15
	mtmsr	r5
	isync

	/* r5 = serial port address */
	LOADPTR(r5, 0xfc004500)

	/* Init serial port */
	
	/* UDCR=0x00 default UART1 mode
	     UART1 interrupt to CPU */
	li     r6, 0x00
	stb   r6, 11(r5)

	/* ULCR=0x80 open DLAB*/
	li	r6, 0x80
	stb	r6, 3(r5)

    /* UAFR=0x00 */
	li      r6, 0x00
	stb   r6, 2(r5)

	/* UDMB=0x02 UDLB=0x8b set baud rate 38400*/
	li	r6, 0xa3
	stb	r6, 0(r5)
	li	r6, 0x00
	stb	r6, 1(r5)

	/* ULCR=0x03 clear DLAB */
	li	r6, 0x03
	stb	r6, 3(r5)

	/* UIRE=0x00 disable interrupt */
	li	r6, 0x00
	stb	r6, 1(r5) 

	
	/* Wait for transmit buffer available */
sowait:
    lbz	r6, 5(r5)
	andi.	r0, r6, 0x40
	bc	12, 2, sowait

	/* Transmit byte */
	stb	r3, 0(r5)

	/* intUnlock(r4) */
	rlwinm	r4,r4,0,16,16
	mfmsr	r5
	or	r4,r4,r5
	mtmsr	r4
	isync

    blr
/*QDIMCZH debug end*/