sp.h

cpc-1631的BSP包for VxWorks操作系统

/* sp.h - sandpoint 8240/7400/7410/755 board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/* Copyright 1996, 1998 Motorola, Inc. */

/*
modification history
--------------------
01k,25mar02,pcs  Add CPU_TYPE_7455
01j,21jan02,pcs  Add CPU_TYPE for 745.
01i,06nov01,jnz  exclude ideDrv.h
01h,16sep01,dat  Use of WRS_ASM macro
01g,15may01,pch  Rename local floppy driver to fix clash with generic in
                 project facility 
01f,01may01,mil  Added CPU_TYPE_7450
01e,24apr01,kab  fixed fdDrv prototype to match system header
01d,09apr01,mil  Added CPU_TYPE_7410
01c,15mar01,kxb  Merge of Sekhar's mods.
01b,12sep00,ksn  added CPU_TYPE_7400 (teamF1)
01a,10oct99,mtl  written from SPS/Motorola & yk 750 by teamF1
*/

/*
This file contains I/O addresses and related constants for the
Sandpoint BSP.
*/

#ifndef	__INCsph
#define	__INCsph

#ifdef __cplusplus
extern "C" {
#endif

#include "drv/pcmcia/pccardLib.h"	/* helps ATA support */
#include "ataDrv.h"		/* help ATA support */
#ifdef INCLUDE_IDE
#	include "drv/hdisk/ideDrv.h"	/* help IDE support */
#endif /* INCLUDE_IDE */

/* BSP defines */

#define SANDPOINT_BSP			/* enable BSP specific features */
#define BUS             	PCI     /* PCI bus interface */

/*
 * These are DUMMY defines used as arguments for dcattach(). They're not
 * used for anything since we replace them with numbers determined
 * dynamically depending on the address MAP, see sysNet.c/sysEnd.c
 */

#define INT_VEC_DC              9       /* interrupt vector PCI slot 2 */
#define INT_LVL_DC              9       /* interrupt level PCI slot 2 */
#define DC_POOL_ADRS            (NONE)  /* NONE = allocate from mem */
#define DC_POOL_SIZE            (NONE)  /* memory pool size use default */
#define DC_DATA_WIDTH           (NONE)  /* all data widths */
#define IO_ADRS_DC              (char *)(0x80000000) /* I/O adrs MAP B */
#define DC_RAM_PCI_ADRS         (0x00000000) /* RAM seen from PCI MAP B */
#define DC_MODE  		0x8            /* default mode */

/*vt82c686B south bridge*/
#define vt82c686PciConfAddr  (PCI_MSTR_ISA_IO_LOCAL +0xcf8)
#define vt82c686PciConfData  (PCI_MSTR_ISA_IO_LOCAL +0xcfc)


/* vt82c686 via defines */

#define	PIC_REG_ADDR_INTERVAL	1	/* adrs diff of adjacent regs. */
#define PCI_ID_IBC              0x06861106      /* Id for vt82c686 PIB */
#define PCI_ID_IDE              0x05711106      /* Id for vt82c686 IDE */

/* PCI Bus function and device for the W83C553 on the Sandpoint */

#define WB_PCI_DEV		0xb		/* Device 11 */
#define WB_PCI_BUS		0x0		/* Bus zero */
#define WB_PCI_FUNC		0x0		/* function zero */
#define WB_PCI_IDEFUNC		0x1		/* IDE is function one */

/* Winbond regs not in sl82565Intr.[ch] */

#define WB_PCI_CTRL_INDX	0x40
#define WB_PCI_CLK_DIV_INDX	0x4c		/* WB clk div reg  */
#define WB_CHIPSEL_CTRL_INDX	0x4d		/* WB chip select ctrl */
#define WB_RSTDRV_BIT		(0x1 << 0x3)	/* PCI/ISA RSTDRV bit */
#define WB_FLASHWRITE_OFF 	(0x1 << 0x5)	/* Flash write disable */
#define WB_EXT_BIOS_ENABLE 	(0x1 << 0x7)	/* BIOS Enabled. */
#define WB_READ_AHEAD_EN	(0x1 << 0x1)	/* read ahead enable */
#define WB_POSTED_WRITE_EN	(0x1 << 0x2)	/* Posted write enable */
#define WB_EARLY_SUB_DECODE	(0x1 << 0x3)	/* early subtractive decode */

#define WB_PCI_CTRL_REG		(WB_POSTED_WRITE_EN  | 		\
				 WB_EARLY_SUB_DECODE |		\
				 WB_READ_AHEAD_EN)

/* floppy support */

#define FD_MAX_DRIVES   	4
#define FD_BASE_ADDR    	(PCI_MSTR_ISA_IO_LOCAL + 0x03f0)

#if FALSE		/* remove this after PCI/ISA RST problem is fixed */
#define FD_DMA_CHAN     	2
#define FD_INT_VEC 		(6 + INT_VEC_IRQ0)
#define FD_INT_LVL 		(6 + INT_NUM_IRQ0)
#else
#define FD_DMA_CHAN     	NONE
#define FD_INT_VEC 		NONE
#define FD_INT_LVL 		NONE
#endif
    
#define WB_ISA_PCI_DECODER_CTRL		0x48
#define WB_ISA_PCI_DECODER_CTRL_VAL	0xf1

#ifdef	INCLUDE_FDC
#   ifndef	INCLUDE_DOSFS
#       define	INCLUDE_DOSFS	/* file system to be used */
#   endif
#   ifndef	INCLUDE_ISADMA
#       define	INCLUDE_ISADMA	/* uses ISA DMA driver */
#   endif
#   ifndef _ASMLANGUAGE
#	include "blkIo.h"
	/* to stop compiler warnings */
	IMPORT STATUS	fdcDrv (UINT, UINT);
	IMPORT BLK_DEV*	fdcDevCreate (UINT, UINT, UINT, UINT);
#   endif
#endif /* INCLUDE_FDC */

/* IDE support defines */
#ifdef	INCLUDE_IDE

#    define IDE_INT_LVL	(0x0e + INT_NUM_IRQ0)	/* IDE cntrlr int level */
#    define IDE_INT_VEC	(IDE_INT_LVL + INT_VEC_IRQ0)	/* IDE int vector */
#endif
    
/* ATA/EIDE support defines */

#ifdef	INCLUDE_ATA_686

#define IDE_CNTRLR0_INT_LVL	(0x0e + INT_NUM_IRQ0)	/* ATA/EIDE cntrlr 0 int level */
#define IDE_CNTRLR1_INT_LVL	(0x0f + INT_NUM_IRQ0)	/* ATA/EIDE cntrlr 1 int level */

/* 
 * below we use the pre-processor to determine the number of ATA devices 
 * to probe on each controller.  This is setup by the user in config.h
 * If the ATA_DEVx_STATE is ATA_DEV_PRESENT then the drive is probed.
 */

#if ((ATA_DEV0_STATE == ATA_DEV_PRESENT) && 		\
         (ATA_DEV1_STATE == ATA_DEV_PRESENT))
#define ATA_CTRL0_DRIVES 2

#elif ((ATA_DEV0_STATE == ATA_DEV_PRESENT) && 		\
           (ATA_DEV1_STATE == ATA_DEV_NOT_PRESENT))
#define ATA_CTRL0_DRIVES 1

#elif ((ATA_DEV0_STATE == ATA_DEV_NOT_PRESENT) && 		\
           (ATA_DEV1_STATE == ATA_DEV_NOT_PRESENT))
#define ATA_CTRL0_DRIVES 0
#endif


#if ((ATA_DEV2_STATE == ATA_DEV_PRESENT) && 		\
         (ATA_DEV3_STATE == ATA_DEV_PRESENT))
#define ATA_CTRL1_DRIVES 2

#elif ((ATA_DEV2_STATE == ATA_DEV_PRESENT) && 		\
           (ATA_DEV3_STATE == ATA_DEV_NOT_PRESENT))
#define ATA_CTRL1_DRIVES 1

#elif ((ATA_DEV2_STATE == ATA_DEV_NOT_PRESENT) && 		\
           (ATA_DEV3_STATE == ATA_DEV_NOT_PRESENT))
#define ATA_CTRL1_DRIVES 0
#endif

#define	ATA_DEV_PRESENT		1	/* Drive does exist */
#define	ATA_DEV_NOT_PRESENT	0	/* Drive does not exist */

#endif	/* INCLUDE_ATA_686 */

/* COM (serial) PORT DEFINITIONS */

#define COM1_ADR        	0x03f8		/* Serial port com1 */
#define COM2_ADR        	0x02f8		/* Serial port com2 */

#define LPT_ADR    0x378

/* parallel port (LPT) */

#define LPT0_BASE_ADRS		0xfe000000+0x378
#define LPT1_BASE_ADRS		0xfe000000+0x3bc
#define LPT2_BASE_ADRS		0xfe000000+0x278
#define LPT0_INT_LVL            INT_NUM_IRQ0+0x05
#define LPT1_INT_LVL            INT_NUM_IRQ0+0x07
#define LPT2_INT_LVL            INT_NUM_IRQ0+0x09
#define INT_NUM_LPT0          INT_NUM_IRQ0+0x05
#define INT_NUM_LPT1          INT_NUM_IRQ0+0x07
#define INT_NUM_LPT2         INT_NUM_IRQ0+0x09
#define LPT_INT_LVL             INT_NUM_IRQ0+0x05
#define LPT_CHANNELS		1


#define VTSB_BUS 0
#define VTSB_DEV 15
#define VTSB_ISA_FUNC 0
#define VTSB_IDE_FUNC 1
#define VTSB_USB_FUNC_01 2
#define VTSB_USB_FUNC_23 3

#define E2_EPP 2
#define E2_S1 (1<<2)
#define E2_S2 (1<<3)
#define E2_FLOPPY (1<<4)

#define IRQ_ROUTE_REG1 0x51
#define IRQ_ROUTE_REG2 0x52
#define IRQ_ROUTE_REG4 0x55
#define IRQ_ROUTE_REG5 0x56
#define IRQ_ROUTE_REG6 0x57
#define PCI_IRQ_TYPE_REG 0x54
#define IRQ(x) x
#define PARALLEL_IRQ 	(IRQ(5)<<4)
#define FLOPPY_IRQ 		(IRQ(6))
#define COM1_IRQ 		(IRQ(4))
#define COM2_IRQ 		(IRQ(3)<<4)
#define PCIA_IRQ		(IRQ(10)<<4)
#define PCIB_IRQ		(IRQ(11))
#define PCIC_IRQ		(IRQ(12)<<4)
#define PCID_IRQ		(IRQ(13)<<4)

#define SUPERIO_CFG_REG 0x85

/* These are dynamically setup for MAP A or MAP B */

#define COM1_BASE_ADR_DYN	(PCI_MSTR_ISA_IO_LOCAL + COM1_ADR)
#define COM2_BASE_ADR_DYN	(PCI_MSTR_ISA_IO_LOCAL + COM2_ADR)

#define N_UART_CHANNELS 	2       	/* 2 serial ports  */
#define N_SIO_CHANNELS  	N_UART_CHANNELS	/* 2 serial I/O channels */

#define COM1_INT_LVL    (0x04 + INT_NUM_IRQ0)   /* com1 interrupt level  */
#define COM2_INT_LVL    (0x03 + INT_NUM_IRQ0)   /* com2 interrupt level  */
#define COM1_INT_VEC    ((COM1_INT_LVL-INT_NUM_IRQ0) + INT_VEC_IRQ0)
#define COM2_INT_VEC    ((COM2_INT_LVL-INT_NUM_IRQ0) + INT_VEC_IRQ0)
#define UART_REG_ADDR_INTERVAL  1    /* distance between ports */


/* 
 * PCI Section.  This is a bit complex since some values are assigned 
 * values dynamically in sysLib.c,sysMemMapDetect().  This is to support
 * either PReP or CHRP mapping, however only CHRP has been tested.
 */

/* PCI/ISA IO space */

#define PCI_MSTR_ISA_IO_LOCAL	sysPciMstrIsaIoLocal 	/* CPU PCI/ISA IO */
#define PCI_MSTR_ISA_IO_LOCAL_A	0x80000000  
#define PCI_MSTR_ISA_IO_LOCAL_B	0xfe000000  
#define PCI_MSTR_ISA_IO_SIZE	0x00010000 
#define PCI_MSTR_ISA_IO_BUS     0  			/* PCI Bus view */

/* PCI CONFIG_ADDR & CONFIG_DATA */

#define PCI_MSTR_CNFG_ADRS	sysPciMstrCfgAdrs
#define PCI_MSTR_CNFG_ADRS_A	0x80800000  
#define PCI_MSTR_CNFG_ADRS_B	0xfec00000  
#define PCI_MSTR_CFNG_SIZE	PCI_MSTR_CFNG_SIZE_B  
#define PCI_MSTR_CFNG_SIZE_A	0x00800000  /* 8MB for PREP map */
#define PCI_MSTR_CFNG_SIZE_B	0x00300000  /* 3MB for CHRP map */

/* PCI IO space */

#define PCI_MSTR_IO_LOCAL	sysPciMstrIoLocal 	/* CPU to PCI IO */
#define PCI_MSTR_IO_LOCAL_A	0x81000000  
#define PCI_MSTR_IO_LOCAL_B	0xfe800000  
#define PCI_MSTR_IO_SIZE	0x00100000  		/* 1MB (Adjusted) */
#define PCI_MSTR_IO_BUS		0x00800000  		/* PCI bus view */

/* PCI IACK space (read to generate PCI IACK) */

#define PCI_MSTR_IACK_LOCAL	sysPciMstrIackLocal 	/* CPU to PCI IACK */
#define PCI_MSTR_IACK_LOCAL_A   0xbfffe000  
#define PCI_MSTR_IACK_LOCAL_B	0xfef00000  
#define PCI_MSTR_IACK_SIZE	VM_PAGE_SIZE  		/* for MMU */

/* PCI/ISA memory space */

#define PCI_MSTR_ISA_MEM_LOCAL	sysPciMstrIsaMemLocal /* CPU to PCI/ISA mem */
#define PCI_MSTR_ISA_MEM_LOCAL_A	0xc1000000  
#define PCI_MSTR_ISA_MEM_LOCAL_B	0xfd000000  
#define PCI_MSTR_ISA_MEM_SIZE		0x00100000 

/* PCI (non-prefetchable) memory space */

#define PCI_MSTR_MEMIO_LOCAL	sysPciMstrMemIoLocal /* CPU to PCI memio */
#define PCI_MSTR_MEMIO_LOCAL_A	0xc0000000  
#define PCI_MSTR_MEMIO_LOCAL_B	0x80000000  
#define PCI_MSTR_MEMIO_SIZE	0x01000000 
#define PCI_MSTR_MEMIO_BUS	sysPciMstrMemIoBus   /* PCI bus view */
#define PCI_MSTR_MEMIO_BUS_A	0x01000000
#define PCI_MSTR_MEMIO_BUS_B	0x80000000

/*
 * Slave window that makes local (60x bus) memory visible to PCI
 * devices.
 */

#define PCI_SLV_MEM_LOCAL	sysPciSlvMemLocal /* PCI to CPU memory */
#define PCI_SLV_MEM_LOCAL_A	0x80000000
#define PCI_SLV_MEM_LOCAL_B	0x00000000	
#define PCI_SLV_MEM_SIZE	LOCAL_MEM_SIZE	

/* macro definitions specifically for pciConfigLib and pciAutoConfigLib */

/* pciAutoConfigLib */

#define PCI_MEM_ADRS		0 
#define PCI_MEM_SIZE		0 /* No prefetchable PCI memory support */

/* PCI (non-prefetchable) memory space */

#define PCI_MEMIO_ADRS		(PCI_MSTR_MEMIO_BUS  + PCI_RSRVD_MEM)
#define PCI_MEMIO_SIZE		(PCI_MSTR_MEMIO_SIZE - PCI_RSRVD_MEM)

/* PCI/ISA IO space */

#define PCI_ISA_IO_ADRS		(PCI_MSTR_ISA_IO_BUS  + PCI_RSRVD_ISA_IO)
#define PCI_ISA_IO_SIZE		(PCI_MSTR_ISA_IO_SIZE - PCI_RSRVD_ISA_IO)

/* PCI IO space */

#define PCI_IO_ADRS		(PCI_MSTR_IO_BUS  + PCI_RSRVD_IO)
#define PCI_IO_SIZE		(PCI_MSTR_IO_SIZE - PCI_RSRVD_IO)

#define PCI_LAT_TIMER		0xff	/* default latency timer value */
#ifndef PCI_MAX_BUS
#	define PCI_MAX_BUS	0x3	/* MAX # of PCI buses expected */
#endif PCI_MAX_BUS
#define NUM_PCI_SLOTS		0x4	/* 4 PCI slots: 0 to 3 */

/* Reserved from pciAutoConfig, must be a multiple of VM_PAGE_SIZE */