s3c6400_ohci.c

Samsung公司S3C6400芯片的BSP源码包

	{
		goto InitializeOHCI_Error;
	}

	pPddObject->lpvMemoryObject = pobMem;
	pPddObject->lpvOhcdMddObject = pobOhcd;
	_tcsncpy(pPddObject->szDriverRegKey, szDriverRegKey, MAX_PATH);
	pPddObject->ioPortBase = ioPortBase;
	pPddObject->dwSysIntr = dii.dwSysintr;

	// PCI OHCI support suspend and resume
	if ( hKey!=NULL)
	{
		DWORD dwCapability;
		DWORD dwType;
		DWORD dwLength = sizeof(DWORD);
		if (RegQueryValueEx(hKey, HCD_CAPABILITY_VALNAME, 0, &dwType, (PUCHAR)&dwCapability, &dwLength) == ERROR_SUCCESS)
		{
			HcdMdd_SetCapability(pobOhcd, dwCapability);
			USBH_INF((_T("[USBH:INF] InitializeOHCI() : USB Host Cap : 0x%08x\n"), dwCapability));
		}

		RegCloseKey(hKey);
	}

	USBH_MSG((_T("[USBH] --InitializeOHCI() : Success\n\r")));

	return TRUE;

InitializeOHCI_Error:

	if (g_pSysConReg != NULL)
	{
		DrvLib_UnmapIoSpace((PVOID)g_pSysConReg);
		g_pSysConReg = NULL;
	}

	if (pPddObject->IsrHandle)
	{
		FreeIntChainHandler(pPddObject->IsrHandle);
		pPddObject->IsrHandle = NULL;
	}

	if (pobOhcd)
	{
		HcdMdd_DestroyHcdObject(pobOhcd);
	}

	if (pobMem)
	{
		HcdMdd_DestroyMemoryObject(pobMem);
	}

	if(pPddObject->pvVirtualAddress)
	{
		HalFreeCommonBuffer(&pPddObject->AdapterObject, pPddObject->dwPhysicalMemSize, pPddObject->LogicalAddress, pPddObject->pvVirtualAddress, FALSE);
	}

	pPddObject->lpvMemoryObject = NULL;
	pPddObject->lpvOhcdMddObject = NULL;
	pPddObject->pvVirtualAddress = NULL;

	if ( hKey!=NULL)
	{
		RegCloseKey(hKey);
	}

	USBH_ERR((_T("[USBH:ERR] --InitializeOHCI() : Error\n\r")));

	return FALSE;
}


/* HcdPdd_Init
 *
 *   PDD Entry point - called at system init to detect and configure OHCI card.
 *
 * Return Value:
 *   Return pointer to PDD specific data structure, or NULL if error.
 */
extern DWORD
HcdPdd_Init(
	DWORD dwContext)	// IN - Pointer to context value. For device.exe, this is a string
						// indicating our active registry key.
{
	SOhcdPdd *  pPddObject = malloc(sizeof(SOhcdPdd));
	BOOL        fRet = FALSE;

	USBH_MSG((_T("[USBH] HcdPdd_Init()\n\r")));

	if (pPddObject)
	{
		pPddObject->pvVirtualAddress = NULL;
		InitializeCriticalSection(&pPddObject->csPdd);
		pPddObject->IsrHandle = NULL;
		pPddObject->hParentBusHandle = CreateBusAccessHandle((LPCWSTR)g_dwContext);

		if (pPddObject->hParentBusHandle)
		{
			fRet = InitializeOHCI(pPddObject, (LPCWSTR)dwContext);
		}

		if(!fRet)
		{
			if (pPddObject->hParentBusHandle)
			{
				CloseBusAccessHandle(pPddObject->hParentBusHandle);
			}

			DeleteCriticalSection(&pPddObject->csPdd);
			free(pPddObject);
			pPddObject = NULL;
		}
	}

	return (DWORD)pPddObject;
}


/* HcdPdd_CheckConfigPower
 *
 *    Check power required by specific device configuration and return whether it
 *    can be supported on this platform.  For CEPC, this is trivial, just limit to
 *    the 500mA requirement of USB.  For battery powered devices, this could be
 *    more sophisticated, taking into account current battery status or other info.
 *
 * Return Value:
 *    Return TRUE if configuration can be supported, FALSE if not.
 */
extern BOOL HcdPdd_CheckConfigPower(
	UCHAR bPort,			// IN - Port number
	DWORD dwCfgPower,		// IN - Power required by configuration
	DWORD dwTotalPower)	// IN - Total power currently in use on port
{
	return ((dwCfgPower + dwTotalPower) > 500) ? FALSE : TRUE;
}

extern void HcdPdd_PowerUp(DWORD hDeviceContext)
{
	SOhcdPdd * pPddObject = (SOhcdPdd *)hDeviceContext;

	USBH_MSG((_T("[USBH] HcdPdd_PowerUp()\n\r")));

	HcdMdd_PowerUp(pPddObject->lpvOhcdMddObject);

#ifdef	USE_SRCCLK_EPLL
	//-----------------------
	// Initialize Clock
	// ClkSrc = MOUT_EPLL (96MHz)
	// Divide by 1 (96/2=48MHz)
	// HCLK, SCLK gate pass
	//-----------------------
	g_pSysConReg->CLK_SRC = (g_pSysConReg->CLK_SRC & ~(0x3<<5)) | (0x1<<5);		// UHOST_SEL : MoutEPLL
	g_pSysConReg->CLK_DIV1 = (g_pSysConReg->CLK_DIV1 & ~(0xf<<20)) | (0x1<<20);	// UHOST_RATIO : 96 MHz / (1+1) = 48 MHz
#else
	//-----------------------
	// Initialize Clock
	// ClkSrc = USB_PHY(48MHz)
	// Divide by 1 (48/1=48MHz)
	// HCLK, SCLK gate pass
	//-----------------------
	g_pSysConReg->OTHERS |= (1<<16);	// Set SUB Signal Mask
	g_pSysConReg->CLK_SRC &= ~(0x3<<5);	// UHOST_SEL : 48MHz
	g_pSysConReg->CLK_DIV1 &= ~(0xf<<20);	// UHOST_RATIO : 48 MHz / (0+1) = 48 MHz
#endif

	g_pSysConReg->HCLK_GATE |= (0x1<<29);		// HCLK_UHOST Pass (EVT1)
	g_pSysConReg->SCLK_GATE |= (0x1<<30);		// SCLK_UHOST Pass

	return;
}

extern void HcdPdd_PowerDown(DWORD hDeviceContext)
{
	SOhcdPdd * pPddObject = (SOhcdPdd *)hDeviceContext;

	USBH_MSG((_T("[USBH] HcdPdd_PowerDown()\n\r")));

	HcdMdd_PowerDown(pPddObject->lpvOhcdMddObject);

	g_pSysConReg->HCLK_GATE &= ~(0x1<<29);	// HCLK_UHOST Mask (EVT1)
	g_pSysConReg->SCLK_GATE &= ~(0x1<<30);	// SCLK_UHOST Mask

	return;
}

extern BOOL HcdPdd_Deinit(DWORD hDeviceContext)
{
	SOhcdPdd * pPddObject = (SOhcdPdd *)hDeviceContext;

	USBH_MSG((_T("[USBH] HcdPdd_Deinit()\n\r")));

	if(pPddObject->lpvOhcdMddObject)
	{
		HcdMdd_DestroyHcdObject(pPddObject->lpvOhcdMddObject);
	}

	if(pPddObject->lpvMemoryObject)
	{
		HcdMdd_DestroyMemoryObject(pPddObject->lpvMemoryObject);
	}

	if(pPddObject->pvVirtualAddress)
	{
		HalFreeCommonBuffer(&pPddObject->AdapterObject, pPddObject->dwPhysicalMemSize, pPddObject->LogicalAddress, pPddObject->pvVirtualAddress, FALSE);
	}

	if (pPddObject->IsrHandle)
	{
		FreeIntChainHandler(pPddObject->IsrHandle);
		pPddObject->IsrHandle = NULL;
	}

	if (pPddObject->hParentBusHandle)
	{
		CloseBusAccessHandle(pPddObject->hParentBusHandle);
	}

	free(pPddObject);

	if (g_pSysConReg)
	{
		//-----------------------
		// Deitialize Clock
		// HCLK, SCLK gate Mask
		//-----------------------
		g_pSysConReg->HCLK_GATE &= ~(0x1<<29);		// HCLK_UHOST Mask (EVT1)
		g_pSysConReg->SCLK_GATE &= ~(0x1<<30);		// SCLK_UHOST Mask

		DrvLib_UnmapIoSpace((PVOID)g_pSysConReg);
		g_pSysConReg = NULL;
	}

	return TRUE;
}


extern DWORD HcdPdd_Open(DWORD hDeviceContext, DWORD AccessCode, DWORD ShareMode)
{
	UnusedParameter(hDeviceContext);
	UnusedParameter(AccessCode);
	UnusedParameter(ShareMode);

	return 1; // we can be opened, but only once!
}


extern BOOL HcdPdd_Close(DWORD hOpenContext)
{
	UnusedParameter(hOpenContext);

	return TRUE;
}


extern DWORD HcdPdd_Read(DWORD hOpenContext, LPVOID pBuffer, DWORD Count)
{
	UnusedParameter(hOpenContext);
	UnusedParameter(pBuffer);
	UnusedParameter(Count);

	return (DWORD)-1; // an error occured
}


extern DWORD HcdPdd_Write(DWORD hOpenContext, LPCVOID pSourceBytes, DWORD NumberOfBytes)
{
	UnusedParameter(hOpenContext);
	UnusedParameter(pSourceBytes);
	UnusedParameter(NumberOfBytes);

	return (DWORD)-1;
}


extern DWORD HcdPdd_Seek(DWORD hOpenContext, LONG Amount, DWORD Type)
{
	UnusedParameter(hOpenContext);
	UnusedParameter(Amount);
	UnusedParameter(Type);

	return (DWORD)-1;
}


extern BOOL HcdPdd_IOControl(DWORD hOpenContext, DWORD dwCode, PBYTE pBufIn,
        DWORD dwLenIn, PBYTE pBufOut, DWORD dwLenOut, PDWORD pdwActualOut)
{
	UnusedParameter(hOpenContext);
	UnusedParameter(dwCode);
	UnusedParameter(pBufIn);
	UnusedParameter(dwLenIn);
	UnusedParameter(pBufOut);
	UnusedParameter(dwLenOut);
	UnusedParameter(pdwActualOut);

	return FALSE;
}


// Manage WinCE suspend/resume events

// This gets called by the MDD's IST when it detects a power resume.
// By default it has nothing to do.
extern void HcdPdd_InitiatePowerUp (DWORD hDeviceContext)
{
	USBH_MSG((_T("[USBH] HcdPdd_InitiatePowerUp()\n\r")));

#ifdef	USE_SRCCLK_EPLL
	//-----------------------
	// Initialize Clock
	// ClkSrc = MOUT_EPLL (96MHz)
	// Divide by 1 (96/2=48MHz)
	// HCLK, SCLK gate pass
	//-----------------------
	g_pSysConReg->CLK_SRC = (g_pSysConReg->CLK_SRC & ~(0x3<<5)) | (0x1<<5);		// UHOST_SEL : MoutEPLL
	g_pSysConReg->CLK_DIV1 = (g_pSysConReg->CLK_DIV1 & ~(0xf<<20)) | (0x1<<20);	// UHOST_RATIO : 96 MHz / (1+1) = 48 MHz
#else
	//-----------------------
	// Initialize Clock
	// ClkSrc = USB_PHY(48MHz)
	// Divide by 1 (48/1=48MHz)
	// HCLK, SCLK gate pass
	//-----------------------
	g_pSysConReg->OTHERS |= (1<<16);	// Set SUB Signal Mask
	g_pSysConReg->CLK_SRC &= ~(0x3<<5);	// UHOST_SEL : 48MHz
	g_pSysConReg->CLK_DIV1 &= ~(0xf<<20);	// UHOST_RATIO : 48 MHz / (0+1) = 48 MHz
#endif

	g_pSysConReg->HCLK_GATE |= (0x1<<29);		// HCLK_UHOST Pass (EVT1)
	g_pSysConReg->SCLK_GATE |= (0x1<<30);		// SCLK_UHOST Pass

	return;
}