regctrl_g2d.h

Samsung公司S3C6400芯片的BSP源码包

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// Copyright (c) Microsoft Corporation.  All rights reserved.
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// license agreement under which you licensed this sample source code. If
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//
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
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/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:    regctrl_g2d.h

Abstract:       defines for FIMGSE-2D Graphics Accelerator Register Controller

Notes:
// Header to define the FIMGSE-2D Register Controller class

--*/

#ifndef __REGCTRL_G2D_H__
#define __REGCTRL_G2D_H__

#include <s3c6400_g2d.h>

/*
#define	rG2D_CONTROL             	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x00)
#define	rG2D_INTEN                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x04)
#define	rG2D_FIFO_INT_CON      (S3C6400_BASE_REG_PA_2DGRAPHICS+0x08)
#define	rG2D_INT_PEND_REG		(S3C6400_BASE_REG_PA_2DGRAPHICS+0x0c)
#define	rG2D_DE_STATUS           (S3C6400_BASE_REG_PA_2DGRAPHICS+0x10)

#define	rG2D_FB_BA                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x20)

#define	rG2D_CMDR0                  (S3C6400_BASE_REG_PA_2DGRAPHICS+0x100)
#define	rG2D_CMDR1                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x104)
#define	rG2D_CMDR2                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x108)
#define	rG2D_CMDR3                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x10c)
#define	rG2D_CMDR4                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x110)
#define	rG2D_CMDR5                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x114)
#define	rG2D_CMDR6                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x118)
#define	rG2D_CMDR7                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x11c)

#define	rG2D_COLOR_MODE          (S3C6400_BASE_REG_PA_2DGRAPHICS+0x200)
#define	rG2D_HORI_RES               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x204)

#define	rG2D_SC_WINDOW           (S3C6400_BASE_REG_PA_2DGRAPHICS+0x210)
#define	rG2D_SC_WINDOW_X       (S3C6400_BASE_REG_PA_2DGRAPHICS+0x214)
#define	rG2D_SC_WINDOW_Y         	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x218)

#define	rG2D_CW_LEFT_TOP             (S3C6400_BASE_REG_PA_2DGRAPHICS+0x220)
#define	rG2D_CW_LEFT_TOP_X       	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x224)
#define	rG2D_CW_LEFT_TOP_Y       	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x228)

#define	rG2D_CW_RIGHT_BOTTOM         (S3C6400_BASE_REG_PA_2DGRAPHICS+0x230)
#define	rG2D_CW_RIGHT_BOTTOM_X   	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x234)
#define	rG2D_CW_RIGHT_BOTTOM_Y   	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x238)

#define	rG2D_COORD0              	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x300)
#define	rG2D_COORD0_X               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x304)
#define	rG2D_COORD0_Y               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x308)

#define	rG2D_COORD1              	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x310)
#define	rG2D_COORD1_X               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x314)
#define	rG2D_COORD1_Y               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x318)

#define	rG2D_COORD2              	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x320)
#define	rG2D_COORD2_X               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x324)
#define	rG2D_COORD2_Y               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x328)

#define	rG2D_COORD3              	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x330)
#define	rG2D_COORD3_X               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x334)
#define	rG2D_COORD3_Y               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x338)

#define	rG2D_ROT_OC              	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x340)
#define	rG2D_ROT_OC_X                (S3C6400_BASE_REG_PA_2DGRAPHICS+0x344)
#define	rG2D_ROT_OC_Y                (S3C6400_BASE_REG_PA_2DGRAPHICS+0x348)
#define	rG2D_ROT_MODE               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x34c)
#define	rG2D_ENDIAN_READSIZE     	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x350)

#define	rG2D_X_INCR                  (S3C6400_BASE_REG_PA_2DGRAPHICS+0x400)
#define	rG2D_Y_INCR                  (S3C6400_BASE_REG_PA_2DGRAPHICS+0x404)

#define	rG2D_ROP                 	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x410)

#define	rG2D_ALPHA                   (S3C6400_BASE_REG_PA_2DGRAPHICS+0x420)

#define	rG2D_FG_COLOR                (S3C6400_BASE_REG_PA_2DGRAPHICS+0x500)
#define	rG2D_BG_COLOR                (S3C6400_BASE_REG_PA_2DGRAPHICS+0x504)
#define	rG2D_BS_COLOR                (S3C6400_BASE_REG_PA_2DGRAPHICS+0x508)

#define	rG2D_PATTERN_ADDR            (S3C6400_BASE_REG_PA_2DGRAPHICS+0x600)

#define	rG2D_PAT_OFF_XY          	(S3C6400_BASE_REG_PA_2DGRAPHICS+0x700)
#define	rG2D_PAT_OFF_X               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x704)
#define	rG2D_PAT_OFF_Y               (S3C6400_BASE_REG_PA_2DGRAPHICS+0x708)                                      																																								
#define	rG2D_COLORKEY_CNTL           (S3C6400_BASE_REG_PA_2DGRAPHICS+0x720)	
#define	rG2D_COLORKEY_DR_MIN         (S3C6400_BASE_REG_PA_2DGRAPHICS+0x724)
#define	rG2D_COLORKEY_DR_MAX         (S3C6400_BASE_REG_PA_2DGRAPHICS+0x728)


class RWReg08
{
private:
    volatile UCHAR m_nV;

public:
    UCHAR operator = (UCHAR v)
    {
        m_nV = v;
        return v;
    }
    operator UCHAR()
    {
        return m_nV;
    }
};

class RWReg16
{
private:
    volatile USHORT m_nV;

public:
    USHORT operator = (USHORT v)
    {
        m_nV = v;
        return v;
    }
    operator USHORT()
    {
        return m_nV;
    }
};

class RWReg32
{
private:
    volatile ULONG m_nV;
public:
    ULONG operator = (ULONG v)
    {
        m_nV = v;
        return v;
    }
    operator ULONG()
    {
        return m_nV;
    }
};

#define Outp32(addr, data)	(*(volatile DWORD *)(addr) = (data))
#define Outp16(addr, data)	(*(volatile WORD *)(addr) = (data))
#define Outp8(addr, data)	(*(volatile BYTE *)(addr) = (data))
#define Inp32(addr)			(*(volatile DWORD *)(addr))
#define Inp16(addr)			(*(volatile WORD *)(addr))
#define Inp8(addr)			(*(volatile BYTE *)(addr))
*/

class RegCtrlG2D
{
	public:
		RegCtrlG2D();
		virtual ~RegCtrlG2D();
		
		volatile S3C6400_G2D_REG * m_pG2DReg;
		
/*    unsigned char * m_pREG8;                // Mapped Register Access Window (REG) address
    unsigned short int  * m_pREG16;               // Mapped Register Access Window (REG) address
    unsigned int  * m_pREG32;               // Mapped Register Access Window (REG) address

		void InitSFRMap();

    // inline functions
    void    inline  _memwB_reg(DWORD offset, BYTE value) {*(RWReg08 *)&m_pREG8[offset] = value;};
    BYTE    inline  _memrB_reg(DWORD offset) {return *(RWReg08 *)&m_pREG8[offset];};
    void    inline  _memwW_reg(DWORD offset, WORD value) {*(RWReg16 *)&m_pREG16[offset >> 1] = value;};
    WORD    inline  _memrW_reg(DWORD offset) {return *(RWReg16 *)&m_pREG16[offset >> 1];};
    void    inline  _memwD_reg(DWORD offset, DWORD value) {*(RWReg32 *)&m_pREG32[offset >> 2] = value;};
    DWORD   inline  _memrD_reg(DWORD offset) {return *(RWReg32 *)&m_pREG32[offset >> 2];};
	*/	

};

#endif //__REGCTRL_G2D_H__