s3c6400otgdevice.h

Samsung公司S3C6400芯片的BSP源码包

#define DOEPCTL2 				0xB40		// Device OUT Endpoint 2 Control
#define DIEPINT2 				0x948		// Device IN Endpoint 2 Interrupt
#define DOEPINT2 				0xB48		// Device OUT Endpoint 2 Interrupt
#define DIEPTSIZ2 				0x950		// Device IN Endpoint 2 Transfer Size
#define DOEPTSIZ2 				0xB50		// Device OUT Endpoint 2 Transfer Size
#define DIEPDMA2 				0x954		// Device IN Endpoint 2 DMA Address
#define DOEPDMA2 				0xB54		// Device OUT Endpoint 2 DMA Address
                               
#define DIEPCTL3 				0x960		// Device IN Endpoint 3 Control
#define DOEPCTL3 				0xB60		// Device OUT Endpoint 3 Control
#define DIEPINT3 				0x968		// Device IN Endpoint 3 Interrupt
#define DOEPINT3 				0xB68		// Device OUT Endpoint 3 Interrupt
#define DIEPTSIZ3 				0x970		// Device IN Endpoint 3 Transfer Size
#define DOEPTSIZ3 				0xB70		// Device OUT Endpoint 3 Transfer Size
#define DIEPDMA3 				0x974		// Device IN Endpoint 3 DMA Address
#define DOEPDMA3 				0xB74		// Device OUT Endpoint 3 DMA Address
                                
#define DIEPCTL4 				0x980		// Device IN Endpoint 4 Control
#define DOEPCTL4 				0xB80		// Device OUT Endpoint 4 Control
#define DIEPINT4 				0x988		// Device IN Endpoint 4 Interrupt
#define DOEPINT4 				0xB88		// Device OUT Endpoint 4 Interrupt
#define DIEPTSIZ4 				0x990		// Device IN Endpoint 4 Transfer Size
#define DOEPTSIZ4 				0xB90		// Device OUT Endpoint 4 Transfer Size
#define DIEPDMA4 				0x994		// Device IN Endpoint 4 DMA Address
#define DOEPDMA4 				0xB94		// Device OUT Endpoint 4 DMA Address
                                
#define DIEPCTL5 				0x9A0		// Device IN Endpoint 5 Control
#define DOEPCTL5			 	0xBA0		// Device OUT Endpoint 5 Control
#define DIEPINT5 				0x9A8		// Device IN Endpoint 5 Interrupt
#define DOEPINT5			 	0xBA8		// Device OUT Endpoint 5 Interrupt
#define DIEPTSIZ5 				0x9B0		// Device IN Endpoint 5 Transfer Size
#define DOEPTSIZ5 				0xBB0		// Device OUT Endpoint 5 Transfer Size
#define DIEPDMA5 				0x9B4		// Device IN Endpoint 5 DMA Address
#define DOEPDMA5 				0xBB4		// Device OUT Endpoint 5 DMA Address
                                
#define DIEPCTL6 				0x9C0		// Device IN Endpoint 6 Control
#define DOEPCTL6 				0xBC0		// Device OUT Endpoint 6 Control
#define DIEPINT6 				0x9C8		// Device IN Endpoint 6 Interrupt
#define DOEPINT6 				0xBC8		// Device OUT Endpoint 6 Interrupt
#define DIEPTSIZ6 				0x9D0		// Device IN Endpoint 6 Transfer Size
#define DOEPTSIZ6 				0xBD0		// Device OUT Endpoint 6 Transfer Size
#define DIEPDMA6 				0x9D4		// Device IN Endpoint 6 DMA Address
#define DOEPDMA6 				0xBD4		// Device OUT Endpoint 6 DMA Address
                                	
#define DIEPCTL7 				0x9E0		// Device IN Endpoint 7 Control
#define DOEPCTL7 				0xBE0		// Device OUT Endpoint 7 Control
#define DIEPINT7 				0x9E8		// Device IN Endpoint 7 Interrupt
#define DOEPINT7 				0xBE8		// Device OUT Endpoint 7 Interrupt
#define DIEPTSIZ7 				0x9F0		// Device IN Endpoint 7 Transfer Size
#define DOEPTSIZ7 				0xBF0		// Device OUT Endpoint 7 Transfer Size
#define DIEPDMA7 				0x9F4		// Device IN Endpoint 7 DMA Address
#define DOEPDMA7 				0xBF4		// Device OUT Endpoint 7 DMA Address
                             	
#define DIEPCTL8 				0xA00		// Device IN Endpoint 8 Control
#define DOEPCTL8 				0xC00		// Device OUT Endpoint 8 Control
#define DIEPINT8 				0xA08		// Device IN Endpoint 8 Interrupt
#define DOEPINT8 				0xC08		// Device OUT Endpoint 8 Interrupt
#define DIEPTSIZ8 				0xA10		// Device IN Endpoint 8 Transfer Size
#define DOEPTSIZ8 				0xC10		// Device OUT Endpoint 8 Transfer Size
#define DIEPDMA8 				0xA14		// Device IN Endpoint 8 DMA Address
#define DOEPDMA8 				0xC14		// Device OUT Endpoint 8 DMA Address
                                		
#define DIEPCTL9 				0xA20		// Device IN Endpoint 9 Control
#define DOEPCTL9 				0xC20		// Device OUT Endpoint 9 Control
#define DIEPINT9 				0xA28		// Device IN Endpoint 9 Interrupt
#define DOEPINT9 				0xC28		// Device OUT Endpoint 9 Interrupt
#define DIEPTSIZ9 				0xA30		// Device IN Endpoint 9 Transfer Size
#define DOEPTSIZ9 				0xC30		// Device OUT Endpoint 9 Transfer Size
#define DIEPDMA9 				0xA34		// Device IN Endpoint 9 DMA Address
#define DOEPDMA9 				0xC34		// Device OUT Endpoint 9 DMA Address
                                
#define DIEPCTL10 				0xA40		// Device IN Endpoint 10 Control
#define DOEPCTL10 				0xC40		// Device OUT Endpoint 10 Control
#define DIEPINT10 				0xA48		// Device IN Endpoint 10 Interrupt
#define DOEPINT10 				0xC48		// Device OUT Endpoint 10 Interrupt
#define DIEPTSIZ10 				0xA50		// Device IN Endpoint 10 Transfer Size
#define DOEPTSIZ10 				0xC50		// Device OUT Endpoint 10 Transfer Size
#define DIEPDMA10 				0xA54		// Device IN Endpoint 10 DMA Address
#define DOEPDMA10 				0xC54		// Device OUT Endpoint 10 DMA Address
                                 
#define DIEPCTL11 				0xA60		// Device IN Endpoint 11 Control
#define DOEPCTL11 				0xC60		// Device OUT Endpoint 11 Control
#define DIEPINT11 				0xA68		// Device IN Endpoint 11 Interrupt
#define DOEPINT11 				0xC68		// Device OUT Endpoint 11 Interrupt
#define DIEPTSIZ11 				0xA70		// Device IN Endpoint 11 Transfer Size
#define DOEPTSIZ11 				0xC70		// Device OUT Endpoint 11 Transfer Size
#define DIEPDMA11 				0xA74		// Device IN Endpoint 11 DMA Address
#define DOEPDMA11 				0xC74		// Device OUT Endpoint 11 DMA Address
                                		
#define DIEPCTL12 				0xA80		// Device IN Endpoint 12 Control
#define DOEPCTL12 				0xC80		// Device OUT Endpoint 12 Control
#define DIEPINT12 				0xA88		// Device IN Endpoint 12 Interrupt
#define DOEPINT12 				0xC88		// Device OUT Endpoint 12 Interrupt
#define DIEPTSIZ12 				0xA90		// Device IN Endpoint 12 Transfer Size
#define DOEPTSIZ12			 	0xC90		// Device OUT Endpoint 12 Transfer Size
#define DIEPDMA12 				0xA94		// Device IN Endpoint 12 DMA Address
#define DOEPDMA12 				0xC94		// Device OUT Endpoint 12 DMA Address
                                 
#define DIEPCTL13 				0xAA0		// Device IN Endpoint 13 Control
#define DOEPCTL13 				0xCA0		// Device OUT Endpoint 13 Control
#define DIEPINT13 				0xAA8		// Device IN Endpoint 13 Interrupt
#define DOEPINT13 				0xCA8		// Device OUT Endpoint 13 Interrupt
#define DIEPTSIZ13 				0xAB0		// Device IN Endpoint 13 Transfer Size
#define DOEPTSIZ13 				0xCB0		// Device OUT Endpoint 13 Transfer Size
#define DIEPDMA13 				0xAB4		// Device IN Endpoint 13 DMA Address
#define DOEPDMA13 				0xCB4		// Device OUT Endpoint 13 DMA Address
                               
#define DIEPCTL14 				0xAC0		// Device IN Endpoint 14 Control
#define DOEPCTL14 				0xCC0		// Device OUT Endpoint 14 Control
#define DIEPINT14 				0xAC8		// Device IN Endpoint 14 Interrupt
#define DOEPINT14 				0xCC8		// Device OUT Endpoint 14 Interrupt
#define DIEPTSIZ14 				0xAD0		// Device IN Endpoint 14 Transfer Size
#define DOEPTSIZ14 				0xCD0		// Device OUT Endpoint 14 Transfer Size
#define DIEPDMA14 				0xAD4		// Device IN Endpoint 14 DMA Address
#define DOEPDMA14 				0xCD4		// Device OUT Endpoint 14 DMA Address
                                
#define DIEPCTL15 				0xAE0		// Device IN Endpoint 15 Control
#define DOEPCTL15 				0xCE0		// Device OUT Endpoint 15 Control
#define DIEPINT15 				0x9E8		// Device IN Endpoint 15 Interrupt
#define DOEPINT15 				0xCE8		// Device OUT Endpoint 15 Interrupt
#define DIEPTSIZ15 				0x9F0		// Device IN Endpoint 15 Transfer Size
#define DOEPTSIZ15 				0xCF0		// Device OUT Endpoint 15 Transfer Size
#define DIEPDMA15 				0x9F4		// Device IN Endpoint 15 DMA Address
#define DOEPDMA15 				0xCF4		// Device OUT Endpoint 15 DMA Address

#define EP0_FIFO					0x1000
#define EP1_FIFO					0x2000
#define EP2_FIFO					0x3000
#define EP3_FIFO					0x4000
#define EP4_FIFO					0x5000
#define EP5_FIFO					0x6000
#define EP6_FIFO					0x7000
#define EP7_FIFO					0x8000
#define EP8_FIFO					0x9000
#define EP9_FIFO					0xa000
#define EP10_FIFO				0xb000
#define EP11_FIFO				0xc000
#define EP12_FIFO				0xd000
#define EP13_FIFO				0xe000
#define EP14_FIFO				0xf000
#define EP15_FIFO				0x10000

//
#define BASE_REGISTER_OFFSET        0x0
#define REGISTER_SET_SIZE           0x200

// Power Reg Bits
#define USB_RESET                   0x8
#define MCU_RESUME                  0x4
#define SUSPEND_MODE                0x2
#define SUSPEND_MODE_ENABLE_CTRL    0x1

// EP0 CSR
#define EP0_OUT_PACKET_RDY          0x1
#define EP0_IN_PACKET_RDY           0x2
#define EP0_SENT_STALL              0x4
#define DATA_END                    0x8
#define SETUP_END                   0x10
#define EP0_SEND_STALL              0x20
#define SERVICED_OUT_PKY_RDY        0x40
#define SERVICED_SETUP_END          0x80

// IN_CSR1_REG Bit definitions
#define IN_PACKET_READY             0x1
#define UNDER_RUN                   0x4   // Iso Mode Only
#define FLUSH_IN_FIFO               0x8
#define IN_SEND_STALL               0x10
#define IN_SENT_STALL               0x20
#define IN_CLR_DATA_TOGGLE          0x40

// OUT_CSR1_REG Bit definitions
#define OUT_PACKET_READY            0x1
#define FLUSH_OUT_FIFO              0x10
#define OUT_SEND_STALL              0x20
#define OUT_SENT_STALL              0x40
#define OUT_CLR_DATA_TOGGLE         0x80

// IN_CSR2_REG Bit definitions
#define IN_DMA_INT_DISABLE          0x10
#define SET_MODE_IN                 0x20 

#define EPTYPE					(0x3<<18)
#define SET_TYPE_CONTROL		(0x0<<18)
#define SET_TYPE_ISO                	(0x1<<18)
#define SET_TYPE_BULK			(0x2<<18)
#define SET_TYPE_INTERRUPT		(0x3<<18)

#define AUTO_MODE                   0x80

// OUT_CSR2_REG Bit definitions
#define AUTO_CLR					0x40
#define OUT_DMA_INT_DISABLE         0x20

// Can be used for Interrupt and Interrupt Enable Reg - common bit def
#define EP0_IN_INT                	(0x1<<0)
#define EP1_IN_INT                	(0x1<<1)
#define EP2_IN_INT                	(0x1<<2)
#define EP3_IN_INT                	(0x1<<3)
#define EP4_IN_INT                	(0x1<<4)
#define EP5_IN_INT               	(0x1<<5)
#define EP6_IN_INT                	(0x1<<6)
#define EP7_IN_INT                	(0x1<<7)
#define EP8_IN_INT                	(0x1<<8)
#define EP9_IN_INT                	(0x1<<9)
#define EP10_IN_INT              	(0x1<<10)
#define EP11_IN_INT             	(0x1<<11)
#define EP12_IN_INT              	(0x1<<12)
#define EP13_IN_INT              	(0x1<<13)
#define EP14_IN_INT              	(0x1<<14)
#define EP15_IN_INT			(0x1<<15)
#define EP0_OUT_INT               (0x1<<16)
#define EP1_OUT_INT               (0x1<<17)
#define EP2_OUT_INT               (0x1<<18)
#define EP3_OUT_INT               (0x1<<19)
#define EP4_OUT_INT               (0x1<<20)
#define EP5_OUT_INT               (0x1<<21)
#define EP6_OUT_INT               (0x1<<22)
#define EP7_OUT_INT               (0x1<<23)
#define EP8_OUT_INT               (0x1<<24)
#define EP9_OUT_INT               (0x1<<25)
#define EP10_OUT_INT             (0x1<<26)
#define EP11_OUT_INT             (0x1<<27)
#define EP12_OUT_INT             (0x1<<28)
#define EP13_OUT_INT             (0x1<<29)
#define EP14_OUT_INT             (0x1<<30)
#define EP15_OUT_INT		(0x1<<31)

// GOTGINT 
#define SesEndDet					(0x1<<2)

// GRSTCTL
#define TxFFlsh				(0x1<<5)
#define RxFFlsh				(0x1<<4)
#define INTknQFlsh			(0x1<<3)
#define FrmCntrRst			(0x1<<2)
#define HSftRst				(0x1<<1)
#define CSftRst				(0x1<<0)

// GINTSTS core interrupt register
#define INT_RESUME              			(0x1<<31)
#define INT_SSREQ					(0x1<<30)
#define INT_DISCONN              			(0x1<<29)
#define INT_OUT_EP					(0x1<<19)
#define INT_IN_EP					(0x1<<18)
#define INT_SDE                			(0x1<<13)
#define INT_RESET               			(0x1<<12)
#define INT_SUSPEND             			(0x1<<11)
#define INT_TX_FIFO_EMPTY			(0x1<<5)
#define INT_RX_FIFO_NOT_EMPTY		(0x1<<4)
#define INT_SOF						(0x1<<3)
#define INT_OTG						(0x1<<2)


#define CLEAR_ALL_EP_INTRS        0xffffffff
									
#define  EP_INTERRUPT_DISABLE_ALL   	0x0   // Bits to write to EP_INT_EN_REG - Use CLEAR

// DMA control register bit definitions
#define RUN_OB							0x80
#define STATE							0x70
#define DEMAND_MODE					0x8
#define OUT_DMA_RUN					0x4
#define IN_DMA_RUN						0x2
#define DMA_MODE_EN					0x1


#define REAL_PHYSICAL_ADDR_EP0_FIFO		(0x520001c0) //Endpoint 0 FIFO
#define REAL_PHYSICAL_ADDR_EP1_FIFO		(0x520001c4) //Endpoint 1 FIFO
#define REAL_PHYSICAL_ADDR_EP2_FIFO		(0x520001c8) //Endpoint 2 FIFO
#define REAL_PHYSICAL_ADDR_EP3_FIFO		(0x520001cc) //Endpoint 3 FIFO
#define REAL_PHYSICAL_ADDR_EP4_FIFO		(0x520001d0) //Endpoint 4 FIFO

//#define DMA_BUFFER_BASE					0xAC000000
//#define DMA_PHYSICAL_BASE				0x30000000
//#define DRIVER_GLOBALS_PHYSICAL_MEMORY_START  (DMA_BUFFER_BASE + 0x10000)

// DAINT device all endpoint interrupt register
//#define INT_IN_EP0					(0x1<<0)
//#define INT_OUT_EP0					(0x1<<16)
//#define INT_IN_EP1					(0x1<<1)
//#define INT_OUT_EP3					(0x1<<19)

// GAHBCFG
#define MODE_DMA					(1<<5)
#define MODE_SLAVE					(0<<5)
#define BURST_SINGLE				(0<<1)
#define BURST_INCR					(1<<1)
#define BURST_INCR4					(3<<1)
#define BURST_INCR8					(5<<1)
#define BURST_INCR16				(7<<1)
#define GBL_INT_MASK				(0<<0)
#define GBL_INT_UNMASK				(1<<0)

// For USB DMA
//BOOL InitUsbdDriverGlobals(void);  	//:-)
//void UsbdDeallocateVm(void);	   	//:-)
//BOOL UsbdAllocateVm(void);	   		//:-)
//void UsbdInitDma(int epnum, int bufIndex,int bufOffset);	//:-)


#endif //_S3C6400OTGD_H_