📄 s3c6400otgdevice.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Module Name:
S3C6400OTGD.H
Abstract:
Samsung S3C6400OTG USB Function Platform-Dependent Driver header.
--*/
#ifndef _S3C6400OTGD_H_
#define _S3C6400OTGD_H_
#include <windows.h>
#include <ceddk.h>
#include <usbfntypes.h>
#include <usbfn.h>
#include <devload.h>
#define RegOpenKey(hkey, lpsz, phk) \
RegOpenKeyEx((hkey), (lpsz), 0, 0, (phk))
#ifndef SHIP_BUILD
#define STR_MODULE _T("S3C6400UsbFn!")
#define SETFNAME() LPCTSTR pszFname = STR_MODULE _T(__FUNCTION__) _T(":")
#else
#define SETFNAME()
#endif
#define OTG_LINK_REG_SIZE 0x11000
// "IoBase"=dword:B1800000
// "IoLen"=dword:11000 ; chandolp 1000 --> 10000
typedef struct {
UINT32 OPHYPWR;
UINT32 OPHYCLK;
UINT32 ORSTCON;
}OTG_PHY_REG, *PS_OTG_PHY_REG;
#define GOTGCTL 0x000 // OTG Control & Status
#define GOTGINT 0x004 // OTG Interrupt
#define GAHBCFG 0x008 // Core AHB Configuration
#define GUSBCFG 0x00C // Core USB Configuration
#define GRSTCTL 0x010 // Core Reset
#define GINTSTS 0x014 // Core Interrupt
#define GINTMSK 0x018 // Core Interrupt Mask
#define GRXSTSR 0x01C // Receive Status Debug Read/Status Read
#define GRXSTSP 0x020 // Receive Status Debug Pop/Status Pop
#define GRXFSIZ 0x024 // Receive FIFO Size
#define GNPTXFSIZ 0x028 // Non-Periodic Transmit FIFO Size
#define GNPTXSTS 0x02C // Non-Periodic Transmit FIFO/Queue Status
#define GPVNDCTL 0x034 // PHY Vendor Control
#define GGPIO 0x038 // General Purpose I/O
#define GUID 0x03C // User ID
#define GSNPSID 0x040 // Synopsys ID
#define GHWCFG1 0x044 // User HW Config1
#define GHWCFG2 0x048 // User HW Config2
#define GHWCFG3 0x04C // User HW Config3
#define GHWCFG4 0x050 // User HW Config4
#define HPTXFSIZ 0x100 // Host Periodic Transmit FIFO Size
#define DPTXFSIZ1 0x104 // Device Periodic Transmit FIFO-1 Size
#define DPTXFSIZ2 0x108 // Device Periodic Transmit FIFO-2 Size
#define DPTXFSIZ3 0x10C // Device Periodic Transmit FIFO-3 Size
#define DPTXFSIZ4 0x110 // Device Periodic Transmit FIFO-4 Size
#define DPTXFSIZ5 0x114 // Device Periodic Transmit FIFO-5 Size
#define DPTXFSIZ6 0x118 // Device Periodic Transmit FIFO-6 Size
#define DPTXFSIZ7 0x11C // Device Periodic Transmit FIFO-7 Size
#define DPTXFSIZ8 0x120 // Device Periodic Transmit FIFO-8 Size
#define DPTXFSIZ9 0x124 // Device Periodic Transmit FIFO-9 Size
#define DPTXFSIZ10 0x128 // Device Periodic Transmit FIFO-10 Size
#define DPTXFSIZ11 0x12C // Device Periodic Transmit FIFO-11 Size
#define DPTXFSIZ12 0x130 // Device Periodic Transmit FIFO-12 Size
#define DPTXFSIZ13 0x134 // Device Periodic Transmit FIFO-13 Size
#define DPTXFSIZ14 0x138 // Device Periodic Transmit FIFO-14 Size
#define DPTXFSIZ15 0x13C // Device Periodic Transmit FIFO-15 Size
//*********************************************************************
// Host Mode Registers
//*********************************************************************
// Host Global Registers
#define HCFG 0x400 // Host Configuration
#define HFIR 0x404 // Host Frame Interval
#define HFNUM 0x408 // Host Frame Number/Frame Time Remaining
#define HPTXSTS 0x410 // Host Periodic Transmit FIFO/Queue Status
#define HAINT 0x414 // Host All Channels Interrupt
#define HAINTMSK 0x418 // Host All Channels Interrupt Mask
// Host Port Control & Status Registers
#define HPRT 0x440 // Host Port Control & Status
// Host Channel-Specific Registers #0
#define HCCHAR0 0x500 // Host Channel-0 Characteristics
#define HCSPLT0 0x504 // Host Channel-0 Split Control
#define HCINT0 0x508 // Host Channel-0 Interrupt
#define HCINTMSK0 0x50C // Host Channel-0 Interrupt Mask
#define HCTSIZ0 0x510 // Host Channel-0 Transfer Size
#define HCDMA0 0x514 // Host Channel-0 DMA Address
// Host Channel-Specific Registers #1
#define HCCHAR1 0x520 // Host Channel-1 Characteristics
#define HCSPLT1 0x524 // Host Channel-1 Split Control
#define HCINT1 0x528 // Host Channel-1 Interrupt
#define HCINTMSK1 0x52C // Host Channel-1 Interrupt Mask
#define HCTSIZ1 0x530 // Host Channel-1 Transfer Size
#define HCDMA1 0x534 // Host Channel-1 DMA Address
// Host Channel-Specific Registers #2
#define HCCHAR2 0x540 // Host Channel-2 Characteristics
#define HCSPLT2 0x544 // Host Channel-2 Split Control
#define HCINT2 0x548 // Host Channel-2 Interrupt
#define HCINTMSK2 0x54C // Host Channel-2 Interrupt Mask
#define HCTSIZ2 0x550 // Host Channel-2 Transfer Size
#define HCDMA2 0x554 // Host Channel-2 DMA Address
// Host Channel-Specific Registers #3
#define HCCHAR3 0x560 // Host Channel-3 Characteristics
#define HCSPLT3 0x564 // Host Channel-3 Split Control
#define HCINT3 0x568 // Host Channel-3 Interrupt
#define HCINTMSK3 0x56C // Host Channel-3 Interrupt Mask
#define HCTSIZ3 0x570 // Host Channel-3 Transfer Size
#define HCDMA3 0x574 // Host Channel-3 DMA Address
// Host Channel-Specific Registers #4
#define HCCHAR4 0x580 // Host Channel-4 Characteristics
#define HCSPLT4 0x584 // Host Channel-4 Split Control
#define HCINT4 0x588 // Host Channel-4 Interrupt
#define HCINTMSK4 0x58C // Host Channel-4 Interrupt Mask
#define HCTSIZ4 0x590 // Host Channel-4 Transfer Size
#define HCDMA4 0x594 // Host Channel-4 DMA Address
// Host Channel-Specific Registers #5
#define HCCHAR5 0x5A0 // Host Channel-5 Characteristics
#define HCSPLT5 0x5A4 // Host Channel-5 Split Control
#define HCINT5 0x5A8 // Host Channel-5 Interrupt
#define HCINTMSK5 0x5AC // Host Channel-5 Interrupt Mask
#define HCTSIZ5 0x5B0 // Host Channel-5 Transfer Size
#define HCDMA5 0x5B4 // Host Channel-5 DMA Address
// Host Channel-Specific Registers #6
#define HCCHAR6 0x5C0 // Host Channel-6 Characteristics
#define HCSPLT6 0x5C4 // Host Channel-6 Split Control
#define HCINT6 0x5C8 // Host Channel-6 Interrupt
#define HCINTMSK6 0x5CC // Host Channel-6 Interrupt Mask
#define HCTSIZ6 0x5D0 // Host Channel-6 Transfer Size
#define HCDMA6 0x5D4 // Host Channel-6 DMA Address
// Host Channel-Specific Registers #7
#define HCCHAR7 0x5E0 // Host Channel-7 Characteristics
#define HCSPLT7 0x5E4 // Host Channel-7 Split Control
#define HCINT7 0x5E8 // Host Channel-7 Interrupt
#define HCINTMSK7 0x5EC // Host Channel-7 Interrupt Mask
#define HCTSIZ7 0x5F0 // Host Channel-7 Transfer Size
#define HCDMA7 0x5F4 // Host Channel-7 DMA Address
// Host Channel-Specific Registers #8
#define HCCHAR8 0x600 // Host Channel-8 Characteristics
#define HCSPLT8 0x604 // Host Channel-8 Split Control
#define HCINT8 0x608 // Host Channel-8 Interrupt
#define HCINTMSK8 0x60C // Host Channel-8 Interrupt Mask
#define HCTSIZ8 0x610 // Host Channel-8 Transfer Size
#define HCDMA8 0x614 // Host Channel-8 DMA Address
// Host Channel-Specific Registers #9
#define HCCHAR9 0x620 // Host Channel-9 Characteristics
#define HCSPLT9 0x624 // Host Channel-9 Split Control
#define HCINT9 0x628 // Host Channel-9 Interrupt
#define HCINTMSK9 0x62C // Host Channel-9 Interrupt Mask
#define HCTSIZ9 0x630 // Host Channel-9 Transfer Size
#define HCDMA9 0x634 // Host Channel-9 DMA Address
// Host Channel-Specific Registers #10
#define HCCHAR10 0x640 // Host Channel-10 Characteristics
#define HCSPLT10 0x644 // Host Channel-10 Split Control
#define HCINT10 0x648 // Host Channel-10 Interrupt
#define HCINTMSK10 0x64C // Host Channel-10 Interrupt Mask
#define HCTSIZ10 0x650 // Host Channel-10 Transfer Size
#define HCDMA10 0x654 // Host Channel-10 DMA Address
// Host Channel-Specific Registers #11
#define HCCHAR11 0x660 // Host Channel-11 Characteristics
#define HCSPLT11 0x664 // Host Channel-11 Split Control
#define HCINT11 0x668 // Host Channel-11 Interrupt
#define HCINTMSK11 0x66C // Host Channel-11 Interrupt Mask
#define HCTSIZ11 0x670 // Host Channel-11 Transfer Size
#define HCDMA11 0x674 // Host Channel-11 DMA Address
// Host Channel-Specific Registers #12
#define HCCHAR12 0x680 // Host Channel-12 Characteristics
#define HCSPLT12 0x684 // Host Channel-12 Split Control
#define HCINT12 0x688 // Host Channel-12 Interrupt
#define HCINTMSK12 0x68C // Host Channel-12 Interrupt Mask
#define HCTSIZ12 0x690 // Host Channel-12 Transfer Size
#define HCDMA12 0x694 // Host Channel-12 DMA Address
// Host Channel-Specific Registers #13
#define HCCHAR13 0x6A0 // Host Channel-13 Characteristics
#define HCSPLT13 0x6A4 // Host Channel-13 Split Control
#define HCINT13 0x6A8 // Host Channel-13 Interrupt
#define HCINTMSK13 0x6AC // Host Channel-13 Interrupt Mask
#define HCTSIZ13 0x6B0 // Host Channel-13 Transfer Size
#define HCDMA13 0x6B4 // Host Channel-13 DMA Address
// Host Channel-Specific Registers #14
#define HCCHAR14 0x6C0 // Host Channel-14 Characteristics
#define HCSPLT14 0x6C4 // Host Channel-14 Split Control
#define HCINT14 0x6C8 // Host Channel-14 Interrupt
#define HCINTMSK14 0x6CC // Host Channel-14 Interrupt Mask
#define HCTSIZ14 0x6D0 // Host Channel-14 Transfer Size
#define HCDMA14 0x6D4 // Host Channel-14 DMA Address
// Host Channel-Specific Registers #15
#define HCCHAR15 0x680 // Host Channel-15 Characteristics
#define HCSPLT15 0x684 // Host Channel-15 Split Control
#define HCINT15 0x688 // Host Channel-15 Interrupt
#define HCINTMSK15 0x68C // Host Channel-15 Interrupt Mask
#define HCTSIZ15 0x690 // Host Channel-15 Transfer Size
#define HCDMA15 0x694 // Host Channel-15 DMA Address
//*********************************************************************
// Device Mode Registers
//*********************************************************************
// Device Global Registers
#define DCFG 0x800 // Device Configuration
#define DCTL 0x804 // Device Control
#define DSTS 0x808 // Device Status
#define DIEPMSK 0x810 // Device IN Endpoint Common Interrupt Mask
#define DOEPMSK 0x814 // Device OUT Endpoint Common Interrupt Mask
#define DAINT 0x818 // Device All Endpoints Interrupt
#define DAINTMSK 0x81C // Device All Endpoints Interrupt Mask
#define DTKNQR1 0x820 // Device IN Token Sequence Learning Queue Read 1
#define DTKNQR2 0x824 // Device IN Token Sequence Learning Queue Read 2
#define DVBUSDIS 0x828 // Device VBUS Discharge Time
#define DVBUSPULSE 0x82C // Device VBUS Pulsing Time
#define DTKNQR3 0x830 // Device IN Token Sequence Learning Queue Read 3
#define DTKNQR4 0x834 // Device IN Token Sequence Learning Queue Read 4
#define DIEPCTL 0x900 // Device IN Endpoint 0 Control
#define DOEPCTL 0xB00 // Device OUT Endpoint 0 Control
#define DIEPINT 0x908 // Device IN Endpoint 0 Interrupt
#define DOEPINT 0xB08 // Device OUT Endpoint 0 Interrupt
#define DIEPTSIZ 0x910 // Device IN Endpoint 0 Transfer Size
#define DOEPTSIZ 0xB10 // Device OUT Endpoint 0 Transfer Size
#define DIEPDMA 0x914 // Device IN Endpoint 0 DMA Address
#define DOEPDMA 0xB14 // Device OUT Endpoint 0 DMA Address
// Device Logical Endpoints-Specific Registers
#define DIEPCTL0 0x900 // Device IN Endpoint 0 Control
#define DOEPCTL0 0xB00 // Device OUT Endpoint 0 Control
#define DIEPINT0 0x908 // Device IN Endpoint 0 Interrupt
#define DOEPINT0 0xB08 // Device OUT Endpoint 0 Interrupt
#define DIEPTSIZ0 0x910 // Device IN Endpoint 0 Transfer Size
#define DOEPTSIZ0 0xB10 // Device OUT Endpoint 0 Transfer Size
#define DIEPDMA0 0x914 // Device IN Endpoint 0 DMA Address
#define DOEPDMA0 0xB14 // Device OUT Endpoint 0 DMA Address
#define DIEPCTL1 0x920 // Device IN Endpoint 1 Control
#define DOEPCTL1 0xB20 // Device OUT Endpoint 1 Control
#define DIEPINT1 0x928 // Device IN Endpoint 1 Interrupt
#define DOEPINT1 0xB28 // Device OUT Endpoint 1 Interrupt
#define DIEPTSIZ1 0x930 // Device IN Endpoint 1 Transfer Size
#define DOEPTSIZ1 0xB30 // Device OUT Endpoint 1 Transfer Size
#define DIEPDMA1 0x934 // Device IN Endpoint 1 DMA Address
#define DOEPDMA1 0xB34 // Device OUT Endpoint 1 DMA Address
#define DIEPCTL2 0x940 // Device IN Endpoint 2 Control
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