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📄 fmd.cpp

📁 Samsung公司S3C6400芯片的BSP源码包
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123 
		case 0:	// No Error
			bRet = TRUE;
			break;
		case 1:	// 1-bit Error(Correctable)
			RETAILMSG(1,(TEXT("%cECC correctable error(0x%x). Byte:%d, bit:%d\r\n"), ((nType==ECC_CORRECT_MAIN)?'M':'S'), sectoraddr, (nRetEcc>>nErrDataNo)&nErrDataMask, (nRetEcc>>nErrBitNo)&nErrBitMask));
			(pData)[(nRetEcc>>nErrDataNo)&nErrDataMask] ^= (1<<((nRetEcc>>nErrBitNo)&nErrBitMask));
			bRet = TRUE;
			break;
		case 2:	// Multiple Error
			RETAILMSG(1,(TEXT("%cECC Uncorrectable error(0x%x)\r\n"), ((nType==ECC_CORRECT_MAIN)?'M':'S'), sectoraddr));
			bRet = FALSE;
			break;
		case 3:	// ECC area Error
			RETAILMSG(1,(TEXT("%cECC area error\r\n"), ((nType==ECC_CORRECT_MAIN)?'M':'S')));
		default:
			bRet = FALSE;
			break;
	}

	return bRet;
}


BOOL FMD_LB_ReadSector(SECTOR_ADDR startSectorAddr, LPBYTE pSectorBuff, PSectorInfo pSectorInfoBuff, DWORD dwNumSectors,int mode)
{
	ULONG SectorAddr = (ULONG)startSectorAddr;
	DWORD       i;
	volatile DWORD		rddata;
	UINT32 nRetEcc = 0;
	DWORD MECCBuf[4];
	UINT16 nSectorLoop;
	int NewSpareAddr = 2048;
	int NewDataAddr = 0;
	int NewSectorAddr = startSectorAddr;
#if CHECK_SPAREECC
	DWORD SECCBuf;
#endif

#if (NAND_DEBUG)
	RETAILMSG(1,(TEXT("#### FMD_DRIVER:::FMD_LB_READSECTOR %x %x\r\n"),startSectorAddr,NewDataAddr));
#endif

	if (!pSectorBuff && !pSectorInfoBuff)
	{
		return(FALSE);
	}

	if ( dwNumSectors > 1 )
	{
		RETAILMSG(1, (TEXT("######## FATAL ERROR => FMD::FMD_ReadSector->dwNumsectors is bigger than 1. \r\n")));
		return FALSE;
	}

	if (!pSectorBuff)
	{
		if (!NAND_LB_ReadSectorInfo(startSectorAddr, pSectorInfoBuff, mode))
		{
			return FALSE;
		}

		return TRUE;
	}

	NF_nFCE_L();

	NF_CLEAR_RB();

	NF_CMD(CMD_READ);							// Send read command.

	NF_ADDR((NewSpareAddr)&0xff);
	NF_ADDR((NewSpareAddr>>8)&0xff);
	NF_ADDR((NewSectorAddr) & 0xff);
	NF_ADDR((NewSectorAddr >> 8) & 0xff);
#if	LB_NEED_EXT_ADDR
	NF_ADDR((NewSectorAddr >> 16) & 0xff);
#endif

	NF_CMD(CMD_READ3);						// 2nd command

	NF_DETECT_RB();								// Wait for command to complete.

	if (pSectorInfoBuff)
	{
#if CHECK_SPAREECC
		NF_RSTECC();
		NF_SECC_UnLock();
#endif

		pSectorInfoBuff->dwReserved1 = NF_RDDATA_WORD();
		pSectorInfoBuff->bOEMReserved = NF_RDDATA_BYTE();
		pSectorInfoBuff->bBadBlock = NF_RDDATA_BYTE();

#if CHECK_SPAREECC
		NF_SECC_Lock();
#endif

		pSectorInfoBuff->wReserved2 = NF_RDDATA_BYTE();
		pSectorInfoBuff->wReserved2 |= (NF_RDDATA_BYTE()<<8);
	}
	else
	{
		 for(i=0; i<sizeof(SectorInfo)/sizeof(DWORD); i++)
		 {
			rddata = (DWORD) NF_RDDATA_WORD();		// read and trash the data
		 }
	}

	for (nSectorLoop = 0; nSectorLoop < SECTORS_PER_PAGE; nSectorLoop++)
	{
		MECCBuf[nSectorLoop] = NF_RDDATA_WORD();
	}

#if CHECK_SPAREECC
	if (pSectorInfoBuff)
	{
		SECCBuf = NF_RDDATA_WORD();
		NF_WRSECCD((SECCBuf&0xff)|((SECCBuf<<8)&0xff0000));

		nRetEcc = NF_ECC_ERR0;

		if (!ECC_CorrectData(startSectorAddr, (LPBYTE)pSectorInfoBuff, nRetEcc, ECC_CORRECT_SPARE))
		{
			return FALSE;
		}
	}
#endif

	for (nSectorLoop = 0; nSectorLoop < SECTORS_PER_PAGE; nSectorLoop++)
	{
		NewDataAddr = nSectorLoop * SECTOR_SIZE;

		NF_CMD(CMD_RDO);							// Send read command.
		NF_ADDR((NewDataAddr)&0xff);
		NF_ADDR((NewDataAddr>>8)&0xff);
		NF_CMD(CMD_RDO2);	// 2nd command

		NF_RSTECC();
		NF_MECC_UnLock();

		if( ((DWORD) (pSectorBuff+nSectorLoop*SECTOR_SIZE)) & 0x3)
		{
			for(i=0; i<SECTOR_SIZE/sizeof(DWORD); i++)
			{
				rddata = (DWORD) NF_RDDATA_WORD();
				(pSectorBuff+nSectorLoop*SECTOR_SIZE)[i*4+0] = (BYTE)(rddata & 0xff);
				(pSectorBuff+nSectorLoop*SECTOR_SIZE)[i*4+1] = (BYTE)(rddata>>8 & 0xff);
				(pSectorBuff+nSectorLoop*SECTOR_SIZE)[i*4+2] = (BYTE)(rddata>>16 & 0xff);
				(pSectorBuff+nSectorLoop*SECTOR_SIZE)[i*4+3] = (BYTE)(rddata>>24 & 0xff);
			}
		}
		else
		{
			RdPage512(pSectorBuff+nSectorLoop*SECTOR_SIZE);					// Read page/sector data.
		}

		NF_MECC_Lock();

		NF_WRMECCD0( ((MECCBuf[nSectorLoop]&0xff00)<<8)|(MECCBuf[nSectorLoop]&0xff) );
		NF_WRMECCD1( ((MECCBuf[nSectorLoop]&0xff000000)>>8)|((MECCBuf[nSectorLoop]&0xff0000)>>16) );

		nRetEcc = NF_ECC_ERR0;

		if (!ECC_CorrectData(startSectorAddr, pSectorBuff+nSectorLoop*SECTOR_SIZE, nRetEcc, ECC_CORRECT_MAIN))
		{
			return FALSE;
		}
	}

	NF_nFCE_H();

	return TRUE;
}

BOOL NAND_LB_ReadSectorInfo(SECTOR_ADDR sectorAddr, PSectorInfo pInfo, int mode)
{
	BOOL bRet = TRUE;
	int NewSpareAddr = 2048;
	int NewSectorAddr = sectorAddr;
#if CHECK_SPAREECC
	DWORD SECCBuf;
	UINT32 nRetEcc = 0;
#endif

	NF_nFCE_L();

	NF_CLEAR_RB();

	NF_CMD(CMD_READ);							// Send read confirm command.

	NF_ADDR((NewSpareAddr)&0xff);
	NF_ADDR((NewSpareAddr>>8)&0xff);
	NF_ADDR((NewSectorAddr)&0xff);
	NF_ADDR((NewSectorAddr>>8) & 0xff);
#if	LB_NEED_EXT_ADDR
	NF_ADDR((NewSectorAddr >> 16) & 0xff);
#endif

	NF_CMD(CMD_READ3);

	NF_DETECT_RB();

#if CHECK_SPAREECC
	NF_RSTECC();
	NF_SECC_UnLock();
#endif

	pInfo->dwReserved1  = NF_RDDATA_WORD();
	pInfo->bOEMReserved = NF_RDDATA_BYTE();
	pInfo->bBadBlock = NF_RDDATA_BYTE();

#if CHECK_SPAREECC
	NF_SECC_Lock();
#endif

	pInfo->wReserved2 = NF_RDDATA_BYTE();
	pInfo->wReserved2 |= (NF_RDDATA_BYTE()<<8);

#if CHECK_SPAREECC
	SECCBuf = NF_RDSECC();
	NF_WRSECCD((SECCBuf&0xff)|((SECCBuf<<8)&0xff0000));

	nRetEcc = NF_ECC_ERR0;

	bRet = ECC_CorrectData(sectorAddr, (LPBYTE)pInfo, nRetEcc, ECC_CORRECT_SPARE);
#endif

	NF_nFCE_H();

	return bRet;
}

BOOL FMD_SB_ReadSector(SECTOR_ADDR startSectorAddr, LPBYTE pSectorBuff, PSectorInfo pSectorInfoBuff, DWORD dwNumSectors,int mode)
{
	ULONG SectorAddr = (ULONG)startSectorAddr;
	ULONG MECC;
	UINT32 nRet = TRUE;
	UINT32 nRetEcc = 0;

#if (NAND_DEBUG)
	RETAILMSG(1,(TEXT("#### FMD_DRIVER:::FMD_sbreadT \r\n")));
#endif

	if (!pSectorBuff && !pSectorInfoBuff)
	{
		RETAILMSG(1,(TEXT("[FMD:ERR] FMD_SB_ReadSector(0x%08x, 0x%08x) : Invalid Parameter\n\r"), pSectorBuff, pSectorInfoBuff));
		return(FALSE);
	}

	while (dwNumSectors--)
	{
		NF_RSTECC();
		NF_MECC_UnLock();
		NF_nFCE_L();

		if (!pSectorBuff)
		{
			NF_CLEAR_RB();
			NF_CMD(CMD_READ2);			// Send read confirm command.

			NF_ADDR(0);									// Ignored.
			NF_ADDR(SectorAddr		 & 0xff);			// Page address.
			NF_ADDR((SectorAddr >>  8) & 0xff);
#if	SB_NEED_EXT_ADDR
			NF_ADDR((SectorAddr >> 16) & 0xff);
#endif

			NF_DETECT_RB();

			RdPageInfo((PBYTE)pSectorInfoBuff);	// Read page/sector information.

			pSectorInfoBuff++;
		}
		else
		{
			NF_CLEAR_RB();

			NF_CMD(CMD_READ);					// Send read command.

			NF_ADDR(0);									// Column = 0.
			NF_ADDR(SectorAddr		 & 0xff);			// Page address.
			NF_ADDR((SectorAddr >>  8) & 0xff);
#if	SB_NEED_EXT_ADDR
			NF_ADDR((SectorAddr >> 16) & 0xff);
#endif

			NF_DETECT_RB();					// Wait for command to complete.

			if( ((DWORD) pSectorBuff) & 0x3)
			{
				RdPage512Unalign (pSectorBuff);
			}
			else
			{
				RdPage512(pSectorBuff);					// Read page/sector data.
			}

			NF_MECC_Lock();

			if (pSectorInfoBuff)
			{
				RdPageInfo((PBYTE)pSectorInfoBuff);		// Read page/sector information.
				pSectorInfoBuff ++;
			}
			else
			{
				BYTE TempInfo[8];
				RdPageInfo(TempInfo);				   	// Read page/sector information.
			}

			MECC  = NF_RDDATA_BYTE() << 0;
			MECC |= NF_RDDATA_BYTE() << 8;
			MECC |= NF_RDDATA_BYTE() << 16;
			MECC |= (NF_RDMECC0() &0xff000000);
			//MECC |= NF_RDDATA_BYTE() << 24;

			NF_WRMECCD0( ((MECC&0xff00)<<8)|(MECC&0xff) );
	 		NF_WRMECCD1( ((MECC&0xff000000)>>8)|((MECC&0xff0000)>>16) );

	 		nRetEcc = NF_ECC_ERR0;

			switch(nRetEcc & 0x3)
			{
				case 0:	// No Error
					nRet = TRUE;
					break;
				case 1:	// 1-bit Error(Correctable)
					RETAILMSG(1,(TEXT("ECC correctable error(0x%x)\r\n"), SectorAddr));
					(pSectorBuff)[(nRetEcc>>7)&0x7ff] ^= (1<<((nRetEcc>>4)&0x7));
					nRet = TRUE;
					break;
				case 2:	// Multiple Error
					RETAILMSG(1,(TEXT("ECC Uncorrectable error(0x%x)\r\n"), SectorAddr));
					nRet = FALSE;
					break;
				case 3:	// ECC area Error
					RETAILMSG(1,(TEXT("ECC area error\r\n")));
				default:
					nRet = FALSE;
					break;
			}
			pSectorBuff += NAND_SECTOR_SIZE;
		}
		NF_nFCE_H();
		++SectorAddr;
	}

	return(nRet);
}

BOOL FMD_LB_WriteSector(SECTOR_ADDR startSectorAddr, LPBYTE pSectorBuff, PSectorInfo pSectorInfoBuff, DWORD dwNumSectors, int mode)
{
	DWORD   i;
	BOOL    bRet = TRUE;
	volatile DWORD	wrdata;
	DWORD MECCBuf[4];
	UINT16 nSectorLoop;
	int NewSpareAddr = 2048;
	int NewDataAddr = 0;
	int NewSectorAddr = startSectorAddr;
#if CHECK_SPAREECC
	DWORD SECCBuf;
#endif

#if (NAND_DEBUG)
	RETAILMSG(1, (TEXT("FMD::FMD_LB_WriteSector 0x%x \r\n"), startSectorAddr));
#endif

	if (!pSectorBuff && !pSectorInfoBuff)
		return(FALSE);

	if ( dwNumSectors > 1 )
	{
		RETAILMSG(1, (TEXT("######## FATAL ERROR => FMD::FMD_WriteSector->dwNumsectors is bigger than 1. \r\n")));
		return FALSE;
	}

	if (!pSectorBuff)
	{
		NAND_LB_WriteSectorInfo(startSectorAddr, pSectorInfoBuff, mode);
		return TRUE;
	}

	//  Enable Chip
	NF_nFCE_L();

	NF_CLEAR_RB();

	//  Issue command
	NF_CMD(CMD_WRITE);

	//  Setup address
	NF_ADDR((NewDataAddr)&0xff);
	NF_ADDR((NewDataAddr>>8)&0xff);
	NF_ADDR((NewSectorAddr)&0xff);
	NF_ADDR((NewSectorAddr>>8)&0xff);
#if	LB_NEED_EXT_ADDR
	NF_ADDR((NewSectorAddr>>16)&0xff);
#endif

	for (nSectorLoop = 0; nSectorLoop < SECTORS_PER_PAGE; nSectorLoop++)
	{
		//  Initialize ECC register
		NF_RSTECC();
		NF_MECC_UnLock();

		//  Special case to handle un-aligned buffer pointer.
		//
		if( ((DWORD) (pSectorBuff+nSectorLoop*SECTOR_SIZE)) & 0x3)
		{
			//  Write the data
			for(i=0; i<SECTOR_SIZE/sizeof(DWORD); i++)
			{
				wrdata = (pSectorBuff+nSectorLoop*SECTOR_SIZE)[i*4+0];
				wrdata |= (pSectorBuff+nSectorLoop*SECTOR_SIZE)[i*4+1]<<8;
				wrdata |= (pSectorBuff+nSectorLoop*SECTOR_SIZE)[i*4+2]<<16;
				wrdata |= (pSectorBuff+nSectorLoop*SECTOR_SIZE)[i*4+3]<<24;
				NF_WRDATA_WORD(wrdata);
			}
		}
		else
		{
			WrPage512(pSectorBuff+nSectorLoop*SECTOR_SIZE);
		}

		//  Read out the ECC value generated by HW
		NF_MECC_Lock();

		MECCBuf[nSectorLoop] = NF_RDMECC0();
	}

	NF_CMD(CMD_RDI);
	NF_ADDR((NewSpareAddr)&0xff);
	NF_ADDR((NewSpareAddr>>8)&0xff);

	// Write the SectorInfo data to the media
	// NOTE: This hardware is odd: only a byte can be written at a time and it must reside in the
	//       upper byte of a USHORT.
	if(pSectorInfoBuff)
	{
#if CHECK_SPAREECC
		NF_RSTECC();
		NF_SECC_UnLock();
#endif

		//  Write the first reserved field (DWORD)
		NF_WRDATA_WORD(pSectorInfoBuff->dwReserved1);
		NF_WRDATA_BYTE(pSectorInfoBuff->bOEMReserved);
		NF_WRDATA_BYTE(pSectorInfoBuff->bBadBlock);
#if CHECK_SPAREECC
		NF_SECC_Lock();
#endif
		NF_WRDATA_BYTE(pSectorInfoBuff->wReserved2&0xff);
		NF_WRDATA_BYTE((pSectorInfoBuff->wReserved2>>8)&0xff);
	}
	else
	{
		// Make sure we advance the Flash's write pointer (even though we aren't writing the SectorInfo data)
		for(i=0; i<sizeof(SectorInfo)/sizeof(DWORD); i++)
		{
			NF_WRDATA_WORD(0xffffffff);
		}
	}

    //  Write the ECC value to the flash
	NF_WRDATA_WORD(MECCBuf[0]);
	NF_WRDATA_WORD(MECCBuf[1]);
	NF_WRDATA_WORD(MECCBuf[2]);
	NF_WRDATA_WORD(MECCBuf[3]);

#if CHECK_SPAREECC
	if(pSectorInfoBuff)
	{
		SECCBuf = NF_RDSECC();
		NF_WRDATA_WORD(SECCBuf);
	}
#endif

	//  Finish up the write operation
	NF_CMD(CMD_WRITE2);

	//  Wait for RB
	NF_DETECT_RB();	 // Wait tR(max 12us)

	if ( NF_RDSTAT & STATUS_ILLACC )
	{
		RETAILMSG(1, (TEXT("FMD_WriteSector() ######## Error Programming page (Illigar Access) %d!\n"), startSectorAddr));
		g_pNFConReg->NFSTAT =  STATUS_ILLACC;	// Write 1 to clear.
		bRet = FALSE;
	}
	else
	{
		//  Check the status
		NF_CMD(CMD_STATUS);

		if(NF_RDDATA_BYTE() & STATUS_ERROR)
		{
			RETAILMSG(1, (TEXT("FMD_WriteSector() ######## Error Programming page %d!\n"), startSectorAddr));
			bRet = FALSE;
		}
	}

	//  Disable the chip
	NF_nFCE_H();

	return bRet;
}

BOOL NAND_LB_WriteSectorInfo(SECTOR_ADDR sectorAddr, PSectorInfo pInfo, int mode)
{
	BOOL    bRet = TRUE;
	int NewSpareAddr = 2048;
	int NewSectorAddr = sectorAddr;
#if CHECK_SPAREECC
	DWORD SECCBuf;
#endif

	//  Chip enable
	NF_nFCE_L();

	NF_CLEAR_RB();

	//  Write the command
	//  First, let's point to the spare area
	NF_CMD(CMD_WRITE);

	//  Write the address
	NF_ADDR((NewSpareAddr)&0xff);
	NF_ADDR((NewSpareAddr>>8)&0xff);
	NF_ADDR((NewSectorAddr)&0xff);
	NF_ADDR((NewSectorAddr>>8)&0xff);
#if	LB_NEED_EXT_ADDR
	NF_ADDR((NewSectorAddr>>16)&0xff);
#endif


#if CHECK_SPAREECC
	NF_RSTECC();
	NF_SECC_UnLock();
#endif

	//  Now let's write the SectorInfo data
	//
	//  Write the first reserved field (DWORD)
	NF_WRDATA_WORD(pInfo->dwReserved1);
	NF_WRDATA_BYTE(pInfo->bOEMReserved);
	NF_WRDATA_BYTE(pInfo->bBadBlock);
#if CHECK_SPAREECC
	NF_SECC_Lock();
#endif
	NF_WRDATA_BYTE(pInfo->wReserved2&0xff);
	NF_WRDATA_BYTE((pInfo->wReserved2>>8)&0xff);

	NF_WRDATA_WORD(0xffffffff);  // Mecc[0]
	NF_WRDATA_WORD(0xffffffff);  // Mecc[1]
	NF_WRDATA_WORD(0xffffffff);  // Mecc[2]
	NF_WRDATA_WORD(0xffffffff);  // Mecc[3]

#if CHECK_SPAREECC
	SECCBuf = NF_RDSECC();
	NF_WRDATA_WORD(SECCBuf);
#endif
123

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