📄 boot.s
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;
; Copyright (c) 2002 Palmmicro Communications Inc. All rights reserved.
;
; --------------------------------------------------------------------
; Module Name:
;
; boot_cache.s
;
; Abstract:
;
; This code is the start point of the boot code, with MMU & cache enabled.
; This code performs all the initialization required before
; branching to the main C application code. It defines the
; ENTRY point, initializes the Stack Pointers for each mode,
; copies RO code and RW data from ROM to RAM and zero-initializes
; the ZI data areas used by the C code, setup the mapping table
; for MMU, enable MMU & cache.
;
INCLUDE at4x0f.inc
INCLUDE ..\inc\sleep.inc
AREA Boot, CODE, READONLY
; --- Define entry point
ENTRY
Start_Boot
EXPORT Start_Boot
; --- Continue execution from ROM rather than aliased copy at zero
LDR pc, =Instruct_2
MRC p15, 0, r0, c1, c0, 0
LDR r1, =0xffff0078
AND r0, r0, r1
ORR r0, r0, #0x1200
MCR p15, 0, r0, c1, c0, 0
IF :DEF: SYS_IO_CLOCK_RATIO
; *********************************
; add one cycle more wait state
; in RISCINT_WATI1 & RISCINT_WATI2
; *********************************
; RISCINT_WAIT1 += 0x01010101
mov r0, #0x90000000
ldr r1, [r0, #0x10]
ldr r2, =0x01010101
add r1, r1, r2
str r1, [r0, #0x10]
; ;;RISCINT_WAIT2 += 0x01010101
; RISCINT_WAIT2 += 0x02020202
ldr r1, [r0, #0x14]
ldr r2, =0x02020202
add r1, r1, r2
str r1, [r0, #0x14]
IF SYS_IO_CLOCK_RATIO = "1"
; RISCINT_WATI2 += (0x01010101 + 0x01010101)
; mov r0, #0x90000000
; ldr r1, [r0, #0x14]
; ldr r2, =0x01010101
; add r1, r1, r2
; add r1, r1, r2
; str r1, [r0, #0x14]
;set i/o clock equal to system clock
;IOBG_ARB_CLKRATIO = 0x0;
; mov r0, #0xB0000000
; ldr r1, =0x00
; str r1, [r0, #0x810]
;RISCINT_WIDTH = 0x0;
; ldr r0, =0x90000000
; ldr r1, =0x0
; str r1, [r0, #0x18]
; PWR_CLK_RATIO = 0x01111111;
; ldr r0, =0x90060040
; ldr r1, =0x01111111
; str r1, [r0]
ENDIF
IF SYS_IO_CLOCK_RATIO = "4"
;set i/o clock to 1/4 of system clock
;IOBG_ARB_CLKRATIO = 0x03;
; ldr r0, =0xB0000810
; ldr r1, =0x03
; str r1, [r0]
;RISCINT_WIDTH = 0x30;
; ldr r0, =0x90000018
; ldr r1, =0x30
; str r1, [r0]
ENDIF
ENDIF
;enable the auto flush for the post write buffer
mov r0, #0x90000000
mov r1, #2
str r1, [r0]
;PWR_DELAY_CTRL0 = (PWR_DELAY_CTRL0 & ~0x0ffff) | 0x280a;
ldr r0, =0x9006004c
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #0xff00
orr r1, r1, #0x2800
orr r1, r1, #0x0a
str r1, [r0]
; *********************************
; To enable rom boot for ddr,
; we need to config CS0 first
; and then turn on pll
; *********************************
;ROM_CFG_CS0=0x034C0C00; // 8 bits rom controller interface;
ldr r0, =0xa0010000
ldr r1, =0x034f4f00
str r1, [r0]
;ROM_CFG_CS1=0x214C0C00; // 8 bits rom controller interface;
ldr r1, =0x214f4f00
str r1, [r0, #4]
; *********************************
; for each dram type, we have
; different settings
; and bootup sequence
;**********************************
ldr r0, =PWRMGR_BASE
ldr r1, [r0, #PWR_PAD_CTRL_OFFSET]
and r1, r1, #3
IF DRAM_TYPE = "MDDR"
cmp r1, #0
ELSE
cmp r1, #1
ENDIF
bne setsdr
; SM_WAIT = 0x1878
ldr r0, =0x80070004
ldr r1, =0x1878
str r1, [r0]
IF DRAM_TYPE = "DDR16"
INFO 0, "INCLUDING DDR16"
INCLUDE ddr16.s
ELSE
IF DRAM_TYPE = "MDDR"
INFO 0, "INCLUDING MOBILEDDR"
INCLUDE mobileddr.s
ELSE
INFO 0, "INCLUDING DDR32"
INCLUDE ddr32.s
ENDIF
ENDIF
b memdone
setsdr
IF DRAM_TYPE = "SDR16"
INFO 0, "INCLUDING SDRAM16"
INCLUDE sdram16.s
ELSE
INFO 0, "INCLUDING SDRAM32"
INCLUDE sdram32.s
ENDIF
memdone
; ***********************
; DRAM configuration ends
; ***********************
; Determine which reset is it from... PWR_SLEEP_STATUS
ldr r0,=PWRMGR_BASE
ldrb r1,[r0, #PWR_SLEEP_STATUS_OFFSET]
mov r10, r1 ; save the status for testing whether we
and r1, r1, #0x17 ; were in Sleep mode later in the code.
str r1, [r0, #PWR_SLEEP_STATUS_OFFSET] ; then write a zero clear the sleep status bit
; --- Flip the memory map by writing to the ClearResetMap location
; in the Reset and Pause Controller
MOV r0, #1
LDR r1, =RISCINT_BOOT_UP
STR r0, [r1]
tst r10, #0x01 ; Sleep Mode?
bne WakeUpFromSleep
; --- Initialize stack pointer registers
; Enter IRQ mode and set up the IRQ stack pointer
MOV r0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =IRQ_Stack
; Enter FIQ mode and set up the FIQ stack pointer
MOV r0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =FIQ_Stack
; Enter ABT mode and set up the ABT stack pointer
MOV r0, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =ABT_Stack
; Enter UNDEF mode and set up the IRQ stack pointer
MOV r0, #Mode_UNDEF:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =UNDEF_Stack
; Set up the SVC stack pointer last and return to SVC mode
MOV r0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =SVC_Stack
; --- Copy codes to sdram
IMPORT InitRegions
CopyStart
BL InitRegions ; in regioninit.s
;
; Setup memory mapping
;
; --- We initialize MMU page table here
address_init
; initialize Translation Table Base reg
ldr r0, = Page_Table_Base
mcr p15, 0, r0, c2, c0, 0
ldr r11, =TranslationTable ; (r11) = &MemoryMap (save pointer)
mov r10, r0
; Setup 1st level page table (using section descriptor)
; Fill in first level page table entries to create "un-mapped" regions
; from the contents of the MemoryMap array.
;
; (r0) = 1st level page table
; (r11) = ptr to MemoryMap array
mov r1, #0x00000000
add r2, r0, #0x4000 ; clear out 16k
18 str r1, [r0], #4
cmp r0, r2
blo %B18
ldr r0, =CACHE_ATTR
20 mov r1, r11 ; (r1) = ptr to MemoryMap array
25 ldr r2, [r1], #4 ; (r2) = virtual address to map Bank at
ldr r3, [r1], #4 ; (r3) = physical address to map from
ldr r4, [r1], #4 ; (r4) = num MB to map
cmp r4, #0 ; End of table?
beq %F29
ldr r5, =0xFFF00000
and r2, r2, r5 ; VA needs 512MB, 1MB aligned.
and r3, r3, r5 ; PA needs 4GB, 1MB aligned.
add r2, r10, r2, LSR #18 ; set descriptor address
add r3, r0, r3 ; (r3) = section descriptor
28 str r3, [r2], #4
subs r4, r4, #1 ; Decrement number of MB left
addne r3, r3, #0x00100000 ; (r3) = PTE for next physical page
bne %B28 ; Map next MB
b %B25 ; Get next element
29
IF :DEF: MEMORY_MAPPING_WINCE
tst r0, #8
bic r0, r0, #0x0C ; clear cachable & bufferable bits in PTE
add r10, r10, #0x0800 ; (r10) = ptr to 1st PTE for "unmapped uncached space"
bne %B20 ; go setup PTEs for uncached space
ENDIF ; MEMORY_MAPPING_WINCE
; initialize 64M sdram from SDRAM_ALT_BASE as cacheble, write-back-bufferable
ldr r0, = Page_Table_Base
ldr r1, = SDRAM_ALT_BASE
ldr r2, = SDRAM_ALT_BASE + 0xC1E
ldr r4, = 64
add r3, r0, r1, lsr #18
SRAM_loop1
str r2, [r3], #4
add r2, r2, #0x100000
subs r4, r4, #1
bne SRAM_loop1
; initialize 64M sdram from 0xc0000000 as non-cacheble, non-bufferable
ldr r0, = Page_Table_Base
ldr r1, = SDRAM_BASE
ldr r2, = SDRAM_BASE + 0xC12
ldr r4, = 64
add r3, r0, r1, lsr #18
SRAM_loop2
str r2, [r3], #4
add r2, r2, #0x100000
subs r4, r4, #1
bne SRAM_loop2
mov r1, #3
mcr p15, 0, r1, c3, c0, 0 ; domain access control, d0 is manager
; mcr p15, 0, r1, c7, c7, 0 ; Invalidate all cache
mcr p15, 0, r0, c8, c7, 0 ; Invalidate TLB
mcr p15, 0, r1, c7, c10, 4 ; Drain write buffer
; prepare for the jump addr after mmu enabled
LDR R2, InitAddr
MRC p15, 0, R0, c1, c0, 0
ORR R0, R0, #0x1200
ORR R0, R0, #0x7f
MCR p15, 0, R0, c1, c0, 0 ; TURNING ON MMU
; let's switch to Virtual address on SDRAM to finish the initialization
BX R2
IMPORT InitDevice
InitAddr
DCD InitDevice
WakeUpFromSleep
;INT_RISC_MASK = INT_RISC_LEVEL = 0;
ldr r0, =0x90020010
ldr r1, =0x00
str r1, [r0], #4
str r1, [r0], #4
str r1, [r0]
mov r3, #0
mcr p15, 0, r3, c7, c10, 4 ; Drain write buffer
mcr p15, 0, r3, c1, c0, 0 ; ICACHE off
mcr p15, 0, r3, c7, c5, 0 ; and flush
nop
nop
; mcr p15, 0, r3, c1, c0, 0 ; caches off -- MMU off or ID map
mcr p15, 0, r3, c8, c7, 0 ; flush tb's
mcr p15, 0, r3, c7, c7, 0 ; flush caches
;
; mcr p15, 0, r0, c15, c1, 2 ; enable clock switching
nop
nop
ldr r5,=SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep
; mode info data structure
ldr r1, [r5, #SLEEP_CHIPREG_SIZE]
mov r3, r5 ; pointer for checksum calculation
ldr r0, =SLEEP_CHECKSUM_SEED
ldr r2, =SLEEP_ARMREG_SIZE ; get size of data structure to do checksum on
add r2, r2, r1
40
ldr r1, [r3], #4
add r0, r0, r1
mov r0, r0, ROR #31
subs r2, r2, #1
bne %b40
ldr r1,=0x90060010;PWR_SCRATCH_PAD_PHYSICAL
ldr r3, [r1] ; get the Sleep data checksum from the Power Manager Scratch pad register
teq r0, r3 ; compare to what we saved before going to sleep
;47
; bne %B47
movne pc, #0x10000000 ; Not equal, jump to original startup function and cold reboot
ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info
ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info
ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info
ldr r7, [r5, #SleepState_WakeAddr] ; load the LR address
mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r9, c2, c0, 0 ; PT address, set up ttb
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mcr p15, 0, r0, c8, c5, 0 ; Invalidate I tlb
mcr p15, 0, r0, c8, c6, 0 ; Invalidate D tlb
; orr r8, r8, #0x1
; mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
; ldc p15, c1, [r5, #SleepState_MMUCTL]
mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
mov pc, r7 ; & jump to new virtual address (back up Power management stack)
nop
nop
nop
INCLUDE memmap.inc
END
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