at4x0f.h

Sirf/Centrality公司GPS平台AtlasIII芯片AT640的Nboot源码

//
// Copyright (c) 2002 Palmmicro Communications Inc.  All rights reserved.
//
// --------------------------------------------------------------------
/*++

Module Name:

  at4x0f.h

Abstract:

  This file defines the registers of palm2 chip.

Notes:

--*/

#ifndef _AT4X0F_H_
#define _AT4X0F_H_


#define IS_DDR()								(1 == (PWR_PAD_CTRL & 3))
#define IS_MDDR()								(0 == (PWR_PAD_CTRL & 3))

#ifndef MEMORY_MAPPING_WINCE

#define SDRAM_BASE                              0xC0000000
#define PERIPHERAL_BASE                         0x80000000
#define SYSTEM_BASE                             0x90000000
#define MEM_CONTROL_BASE                        0xa0000000
#define DMA_CONTROL_BASE                        0xb0000000
#define LCD_BASE                                0xb8000000
#define PCMCIA_SOCKET_1                         0x30000000
#define PCMCIA_SOCKET_O                         0x20000000
#define SIM_BASE                                0xfff00000
#define EXT_PIO_BASE                            0x14000000
#define ROM_ADD_CS0_BASE                        0x10000000
#define PCI_DEVICE_BASE                         0x50000000
#define _DSP_SHARED_MEMORY                      0x48000000

#define _USBOTG_MODULE_BASE                     0x57f00000 // 1  MB USB (io) registers
#define _IDE_MODULE_BASE                        0x57d00000 // 1  MB IDE (io) registers
#define _PCMCIA_MODULE_BASE                     0x57c00000 // 1  MB PCMCIA (io) registers
#define _EPCI_MODULE_BASE                       0x57b00000 // 1  MB External PCI (io) registers
#define _PCI_ROM_MODULE_BASE                    0x57a00000 // 1  MB PCI ROM(io) registers
#define _PCI_COPY_MODULE_BASE                   0x57900000 // 1  MB PCI_COPY(io) register
#define _YUV_CHG_MODULE_BASE                    0x57800000 // 1  MB YUV_CHG(io) register
#define _IPOLATE_MODULE_BASE                    0x57700000 // 1  MB IPOLATE(io) register

#define _SD_MODULE_BASE                         0x56000000 // 1  MB SDIO(io) registers
#define PCMCIA_IO_PHYSICAL_BASE                 0x57C00000

#define ROM_ADD_CS2_BASE                        (ROM_ADD_CS0_BASE + 0x8000000)
#define ROM_ADD_CS3_BASE                        (ROM_ADD_CS0_BASE + 0xC000000)

#define DRIVER_GLOBALS_PHYSICAL_MEMORY_START	0xC0002000
#define _YUVCHG_MODULE_BASE						(_YUV_CHG_MODULE_BASE)
#define _PCICOPY_MODULE_BASE					(_PCI_COPY_MODULE_BASE)
#define _YUVRGB_MODULE_BASE 					0x57600000
#define DSP_MEM_PHYSICAL_BASE					0x48000000
#define _DSP_PM_BASE							(DSP_MEM_PHYSICAL_BASE)
#define _DSP_DM_BASE							(DSP_MEM_PHYSICAL_BASE+0x10000)

#else // MEMORY_MAPPING_WINCE

#define SDRAM_BASE                              0x8C000000
#define PERIPHERAL_BASE                         0xAB000000
#define SYSTEM_BASE                             0xAA000000
#define MEM_CONTROL_BASE                        0xA9000000
#define DMA_CONTROL_BASE                        0xA8000000
#define LCD_BASE                                0xA7000000
#define SIM_BASE                                0xA6000000
#define PCMCIA_SOCKET_1                         0xA4300000
#define PCMCIA_SOCKET_O                         0xA4200000
#define EXT_PIO_BASE                            0xA4000000
#define ROM_ADD_CS0_BASE                        0xA0000000
#define PCI_DEVICE_BASE                         0x50000000
#define _DSP_SHARED_MEMORY                      0xA5000000
#define _PCI_COPY_MODULE_BASE                   0xA5700000 // 1  MB PCI_COPY(io) register
#define _USBOTG_MODULE_BASE                     0xA5600000 // 1  MB USB (io) registers
#define _IDE_MODULE_BASE                        0xA5500000 // 1  MB IDE (io) registers
#define _PCMCIA_MODULE_BASE                     0xA5400000 // 1  MB PCMCIA (io) registers
#define _EPCI_MODULE_BASE                       0xA5300000 // 1  MB External PCI (io) registers
#define _PCI_ROM_MODULE_BASE                    0xA5200000 // 1  MB PCI ROM(io) registers
#define _SD_MODULE_BASE                         0xA5100000 // 1  MB SDIO(io) registers

#define ROM_ADD_CS2_BASE                        0xA2000000
#define ROM_ADD_CS3_BASE                        0xA1000000

#define DRIVER_GLOBALS_PHYSICAL_MEMORY_START	0xAC002000

#endif // MEMORY_MAPPING_WINCE

#define ROM_ADD_CS1_BASE                        EXT_PIO_BASE

#define _RISC_MODULE_BASE                       (SYSTEM_BASE)
#define _DSP_MODULE_BASE                        (SYSTEM_BASE + 0x10000)
#define _INT_MODULE_BASE                        (SYSTEM_BASE + 0x20000)
#define _RSC_MODULE_BASE                        (SYSTEM_BASE + 0x30000)
#define _RTC_MODULE_BASE                        (SYSTEM_BASE + 0x40000)
#define _OST_MODULE_BASE                        (SYSTEM_BASE + 0x50000)
#define _POWER_MODULE_BASE                      (SYSTEM_BASE + 0x60000)
#define _RESET_MODULE_BASE                      (SYSTEM_BASE + 0x70000)

#define _MEMORY_MODULE_BASE                     (MEM_CONTROL_BASE)
#define _ROM_MODULE_BASE                        (MEM_CONTROL_BASE + 0x10000)
#define _ARBITER_MODULE_BASE                    (MEM_CONTROL_BASE + 0x20000)

#define _GPIO_MODULE_BASE                       (PERIPHERAL_BASE + 0x90000)
#define _SER0_MODULE_BASE                       (PERIPHERAL_BASE + 0x00000)
#define _SER1_MODULE_BASE                       (PERIPHERAL_BASE + 0x10000)
#define _SER2_MODULE_BASE                       (PERIPHERAL_BASE + 0x20000)
#define _SER3_MODULE_BASE                       (PERIPHERAL_BASE + 0x30000)
#define _SER4_MODULE_BASE                       (PERIPHERAL_BASE + 0x40000)
#define _SER5_MODULE_BASE                       (PERIPHERAL_BASE + 0x50000)
//added uart6,7 yjliao
#define _SER6_MODULE_BASE  		  	(PERIPHERAL_BASE + 0x100000)
#define _SER7_MODULE_BASE  	              (PERIPHERAL_BASE + 0x110000)

#define _CODEC_MODULE_BASE                      (PERIPHERAL_BASE + 0x60000)
#define _SMDF_MODULE_BASE                       (PERIPHERAL_BASE + 0x70000)
#define _CAM_MODULE_BASE                        (PERIPHERAL_BASE + 0x80000)
#define _HOST_MODULE_BASE                       (PERIPHERAL_BASE + 0x90000)
#define _GPS_MODULE_BASE                        (PERIPHERAL_BASE + 0xa0000)
#define _PCI_MODULE_BASE                        (PERIPHERAL_BASE + 0xc0000)
#define _CAN0_MODULE_BASE                       (PERIPHERAL_BASE + 0xd0000)
#define _CAN1_MODULE_BASE                       (PERIPHERAL_BASE + 0xe0000)
#define _PWM_MODULE_BASE                        (PERIPHERAL_BASE + 0xf0000)

#define _DMA_MODULE_BASE                        DMA_CONTROL_BASE
#define _LCD_MODULE_BASE                        LCD_BASE

/***************************************************************************************\
| Risc interface registers
\***************************************************************************************/
#define RISCINT_FIFO_FLUSH                      (*(volatile DWORD *)_RISC_MODULE_BASE)
#define RISCINT_MEM_SIZE                        (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x0004))
#define RISCINT_ROM_SIZE                        (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x0008))
#define RISCINT_BOOT_UP                         (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x000c))
#define RISCINT_WAIT1                           (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x0010))
#define RISCINT_WAIT2                           (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x0014))
#define RISCINT_WIDTH                           (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x0018))
#define RISCINT_TIMEOUT                         (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x001C))
#define RISCINT_TIMEOUT_INT                     (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x0020))
#define RISCINT_PREFETCH_EN                     (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x0024))
#define RISCINT_PCIROM_EN                       (*(volatile DWORD *)(_RISC_MODULE_BASE + 0x0028))

/***************************************************************************************\
| Interrupt controller registers
\***************************************************************************************/
#define INT_PENDING                             (*(volatile DWORD *)_INT_MODULE_BASE)
#define INT_IRQ_PENDING                         (*(volatile DWORD *)(_INT_MODULE_BASE + 0x0004))
#define INT_FIQ_PENDING                         (*(volatile DWORD *)(_INT_MODULE_BASE + 0x0008))
#define INT_DSP0_PENDING                        (*(volatile DWORD *)(_INT_MODULE_BASE + 0x000c))
#define INT_RISC_MASK                           (*(volatile DWORD *)(_INT_MODULE_BASE + 0x0010))
#define INT_DSP_MASK                            (*(volatile DWORD *)(_INT_MODULE_BASE + 0x0014))
#define INT_RISC_LEVEL                          (*(volatile DWORD *)(_INT_MODULE_BASE + 0x0018))