power.h

Sirf/Centrality公司GPS平台AtlasIII芯片AT640的Nboot源码

//
// Copyright (c) 2002 Palmmicro Communications Inc.  All rights reserved.
//
// --------------------------------------------------------------------
/*++

Module Name:

  power.h

Abstract:

  This file defines the bitmask of power management module.

Notes:

--*/
#ifndef _PALM3_POWER_H_
#define _PALM3_POWER_H_

#define PWR_CLOCK_ENABLE(x)		(PWR_CLK_EN |= (x))
#define PWR_CLOCK_DISABLE(x)	(PWR_CLK_EN &= ~(x))

/*
**	bitmask for PWR_CLK_EN
*/
#define PWRCLK_DSP_EN       (1 << 0)    //  DSP Core clock enable
#define PWRCLK_ROM_EN       (1 << 1)    //  Flash Controller clock enable
#define PWRCLK_DMA_EN       (1 << 2)    //  DMA Controller clock enable
#define PWRCLK_LCD_EN       (1 << 3)    //  LCD Controller clock enable.
#define PWRCLK_GPS_EN       (1 << 4)    //  GPS clock enable.
#define PWRCLK_USB_EN       (1 << 5)    //  USB OTG clock enable.
#define PWRCLK_PCMCIA_EN    (1 << 6)    //  PCMCIA Core clock enable.
#define PWRCLK_CAM_EN       (1 << 7)    //  Camera clock enable.
#define PWRCLK_CODEC_EN     (1 << 8)    //  CODEC clock enable
#define PWRCLK_UART_EN      (1 << 9)    //  UART (SP0, 6, & 7) clock enable
#define PWRCLK_SP1_EN       (1 << 10)   //  Serial Port 1 clock enable
#define PWRCLK_SP2_EN       (1 << 11)   //  Serial Port 2 clock enable
#define PWRCLK_SP3_EN       (1 << 12)   //  Serial Port 3 clock enable
#define PWRCLK_SP4_EN       (1 << 13)   //  Serial Port 4 clock enable
#define PWRCLK_SP5_EN       (1 << 14)   //  Serial Port 5 clock enable
#define PWRCLK_IPOLATE_EN   (1 << 15)   //  Interpolation block clock enable
#define PWRCLK_EXT_EN       (1 << 16)   //  Extension port clock enable
#define PWRCLK_SDIO_EN      (1 << 17)   //  SDIO interface clock enable
#define PWRCLK_SM_EN        (1 << 18)   //  SmartMedia interface clock enable
#define PWRCLK_COPY_EN      (1 << 19)   //  PCI copy block clock enable
#define PWRCLK_I2C_EN       (1 << 20)   //  I2C interface clock enable
#define PWRCLK_IO_EN        (1 << 21)   //  I/O clock enable
#define PWRCLK_PCI_EN       (1 << 22)   //  PCI clock enable
#define PWRCLK_CKO0_EN      (1 << 23)   //  Output clock_0 enable
#define PWRCLK_CKO1_EN      (1 << 24)   //  Output clock_1 enable
#define PWRCLK_CAN0_EN      (1 << 25)   //  CAN Bus 0 clock enable
#define PWRCLK_CAN1_EN      (1 << 26)   //  CAN Bus 1 clock enable
#define PWRCLK_PADARB_EN    (1 << 27)   //  Pad arbitration clock enable
#define PWRCLK_XIN_EN       (1 << 28)   //  XIN clock enable
#define PWRCLK_XINW_EN      (1 << 29)   //  XINW clock enable
#define PWRCLK_IDE_EN       (1 << 30)   //  IDE interface clock enable

#define	PWRCLK_SP0_EN		PWRCLK_UART_EN

#endif // #ifndef _PALM3_POWER_H_
/* end of power.h */