flushdc.s

Sirf/Centrality公司GPS平台AtlasIII芯片AT640的Nboot源码

;
; Copyright (c) Centrality Communications Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
; Copyright (c) 1998, 1999 ARM Limited
; All Rights Reserved
;

	EXPORT ARMReadCacheInfo
	EXPORT ARMFlushDCache
	EXPORT ARMFlushDCacheLines
	
	AREA ARMFlushDCache, CODE, READONLY
    
;++
; Routine Description:
;    Clean and invalidate the Data Cache
;
; The following code is called to flush the dcache. It
; does a clean and invalidate on each cache line using the index and
; segment.
;
; Syntax:
;       void ARMFlushDCache(
;           DWORD dwLinesPerSetZeroRel,
;           DWORD dwSetsZeroRel,
;           DWORD dwSetIndexBit,
;           DWORD dwLineSize)
;
; Arguments:
;       dwLinesPerSetZeroRel - 0 relative number of cache lines per set
;       dwSetsZeroRel - 0 relative number of cache sets
;       dwSetIndexBit - 32 - Log2(dwLinesPerSet)
;       dwLineSize - cache line size, in bytes
;
; Return Value:
;       -- none --
; r0..r3,r12 junk
; CC flags junk
;--

    ; save registers
    stmfd   sp!, {r4}
    mov     r4, r1                          ; save the number of sets

clean_indexloop
    mov     r12, r0, lsl r2                 ; index goes in the top 6 bits
    mov     r1, r4                          ; reload number of sets
    
clean_setloop
    ; write back and invalidate the line
    mcr     p15, 0, r12, c7, c14, 2

    ; add the set index
    add     r12, r12, r3

    ; decrement the set number
    subs    r1, r1, #1
    bpl     clean_setloop

    ; decrement the index number
    subs    r0, r0, #1
    bpl     clean_indexloop

    ; drain the write buffer
    mov     r0, #0
    mcr     p15, 0, r0, c7, c10, 4
    
    ; restore registers
    ldmfd   sp!, {r4}

	bx lr

	AREA ARMFlushDCacheLines, CODE, READONLY

;++
; Routine Description:
;    Invalidate some number of Instruction Cache lines
;
; Syntax:
;	void ARMFlushICacheLines(PVOID pAddr, DWORD dwLength, DWORD dwLineLength);
;
; Arguments:
;	pAddr -- virtual address at which to start invalidation, on dwLineLength-byte 
;            alignment
;	dwLength -- number of bytes to invalidate, must be > zero
;   dwLineLength -- number of bytes in a cache line
;
; Return Value:
;	-- none --
; r0..r2 junk
; CC flags junk	
;--

    ; invalidate the range of lines
10
    mcr 	p15, 0, r0, c7, c14, 1  ; clean and invalidate each entry
    add     r0, r0, r2              ; on to the next line
    subs	r1, r1, r2              ; reduce the number of bytes left
    bgt     %b10                    ; loop while > 0 bytes left

    ; load parameter for write buffer drain
    mov     r2, #0
    mcr     p15, 0, r2, c7, c10, 4      ; drain write buffer

	bx lr

	AREA ARMReadCacheInfo, CODE, READONLY

    mrc     p15, 0, r0, c0, c0, 1   ; read the cache info register

	bx lr

    END