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📄 usp.h

📁 Sirf/Centrality公司GPS平台AtlasIII芯片AT640的Nboot源码
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//
// Copyright (c) 2002 Palmmicro Communications Inc.  All rights reserved.
//                                                                     
// --------------------------------------------------------------------
/*++

Module Name:
	
  usp.h
	  
Abstract:
		
  This file defines the bitmasks of the usp module.
		  
Notes:
				
--*/
#ifndef _PALM2_USP_H_
#define _PALM2_USP_H_

#define USP_FIFO_DEPTH                          32



//USP_MODE1 bit fields
#define USP_SYNC_MODE                           0x1
#define USP_CLK_SLAVE_MODE                      0x2
#define USP_LOOP_BACK_EN                        0x4
#define USP_HPSIR_EN                            0x8
#define USP_LITTLE_ENDIAN                       0x10
#define USP_ENABLE                              0x20
#define USP_RX_DATA_EDGE_NEG                    0x40
#define USP_TX_DATA_EDGE_NEG                    0x80
#define USP_RX_SYNC_VALID_HIGH                  0x100
#define USP_TX_SYNC_VALID_HIGH                  0x200
#define USP_SCLK_IDLE_TOGGLE                    0x400
#define USP_SCLK_IDLE_HIGH                      0x800
#define USP_SCLK_AS_GPIO                        0x1000
#define USP_RFS_AS_GPIO                         0x2000
#define USP_TFS_AS_GPIO                         0x4000
#define USP_RXD_AS_GPIO                         0x8000
#define USP_TXD_AS_GPIO                         0x10000
#define USP_SCLK_IO_IN                          0x20000
#define USP_RFS_IO_IN                           0x40000
#define USP_TFS_IO_IN                           0x80000
#define USP_RXD_IO_IN                           0x100000
#define USP_TXD_IO_IN                           0x200000
#define USP_IRDA_RXD_IDEL_HIGH			0x40000000
#define USP_UFLOW_RPT_ZERO			0x80000000


//USP_MODE2 bit fields
#define USP_RX_DATA_DELAY_MASK                  0xff
#define USP_TX_DATA_DELAY_MASK                  0xff00
#define USP_ENA_AUTO_CLEAR                      0x10000
#define USP_FRAME_REPEAT_SEND                   0x20000
#define USP_SOFT_TFS                            0x40000
#define USP_RFS_SLAVE                           0x80000
#define USP_TFS_SLAVE                           0x100000
#define USP_CLK_DIV_MASK                        0x7fe00000
#define USP_IRDA_SHORT_WIDTH			0x80000000
//USP_TX_FRAME_CTRL bit fields
#define USP_TX_DATA_LEN_MASK                    0xff
#define USP_TX_SYNC_LEN_MASK                    0xff00
#define USP_TX_FRAME_LEN_MASK                   0xff0000
#define USP_TX_SHIFTER_LEN_MASK                 0x1f000000
#define USP_GLITCH_FREE_SAMPLE                  0x20000000

//USP_RX_FRAME_CTRL bit fields
#define USP_RX_DATA_LEN_MASK                    0xff
#define USP_RX_FRAME_LEN_MASK                   0xff00
#define USP_RX_SHIFTER_LEN_MASK                 0x1f0000

//USP_TX_RX_ENABLE bit fields
#define USP_RX_EN                               0x01
#define USP_TX_EN                               0x02

//USP_INT_ENABLE, USP_INT_STATUS bit fields
#define USP_INT_RX_DONE_MASK                    0x0001
#define USP_INT_TX_DONE_MASK                    0x0002
#define USP_INT_RX_OF_MASK                      0x0004
#define USP_INT_TX_UF_MASK                      0x0008
#define USP_INT_DMA_RX_MASK                     0x0010
#define USP_INT_DMA_TX_MASK                     0x0020
#define USP_INT_RX_FF_MASK                      0x0040
#define USP_INT_TX_FE_MASK                      0x0080
#define USP_INT_RX_THLD_MASK                    0x0100
#define USP_INT_TX_THLD_MASK                    0x0200
#define USP_INT_FRM_ERR_MASK                    0x0400
#define USP_INT_TIMEOUT_MASK			0x0800
#define USP_INT_TX_ALLEMPTY_MASK		0x1000

//USP_RISC_DSP_MODE bit fields
#define USP_DSP_ACCESS                          0x1

#if(USP_FIFO_DEPTH==16)
	//USP_TX_DMA_IO_CTRL bit fields
	#define USP_TX_IO_MODE                          0x1
	
	//USP_TXFIFO_CTRL bit fields
	#define USP_TXFIFO_WIDTH_BYTE                   0x0
	#define USP_TXFIFO_WIDTH_WORD                   0x1
	#define USP_TXFIFO_WIDTH_DWORD                  0x2
	#define USP_TXFIFO_THLD_MASK                    0x3c
	                                
	//USP_TXFIFO_LEVEL_CHK bit fields
	#define USP_TXFIFO_SC_MASK                      0x3
	#define USP_TXFIFO_LC_MASK                      0xc00
	#define USP_TXFIFO_HC_MASK                      0x300000
	
	//USP_TXFIFO_OP bit fields
	#define USP_TXFIFO_RESET                        0x1             
	#define USP_TXFIFO_START                        0x2
	
	
	//USP_TXFIFO_STATUS bit fields
	#define USP_TXFIFO_LEVEL_MASK                   0x1f
	#define USP_TXFIFO_FULL                         0x10
	#define USP_TXFIFO_EMPTY                        0x20
	
	//USP_RX_DMA_IO_CTRL bit fields
	#define USP_RX_IO_MODE                          0x1
	#define USP_RX_FIFO_FLUSH			0x4
	
	//USP_RXFIFO_CTRL bit fields
	#define USP_RXFIFO_WIDTH_BYTE                   0x0
	#define USP_RXFIFO_WIDTH_WORD                   0x1
	#define USP_RXFIFO_WIDTH_DWORD                  0x2
	#define USP_RXFIFO_THLD_MASK                    0x3c
	                                
	//USP_RXFIFO_LEVEL_CHK bit fields
	#define USP_RXFIFO_SC_MASK                      0x3
	#define USP_RXFIFO_LC_MASK                      0xc00
	#define USP_RXFIFO_HC_MASK                      0x300000
	
	//USP_RXFIFO_OP bit fields
	#define USP_RXFIFO_RESET                        0x1
	#define USP_RXFIFO_START                        0x2
	
	//USP_RXFIFO_STATUS bit fields
	#define USP_RXFIFO_LEVEL_MASK                   0x1f
	#define USP_RXFIFO_FULL                         0x10
	#define USP_RXFIFO_EMPTY                        0x20
#else	//32 byte
	//USP_TX_DMA_IO_CTRL bit fields
	#define USP_TX_IO_MODE                          0x1
	
	//USP_TXFIFO_CTRL bit fields
	#define USP_TXFIFO_WIDTH_BYTE                   0x0
	#define USP_TXFIFO_WIDTH_WORD                   0x1
	#define USP_TXFIFO_WIDTH_DWORD                  0x2
	#define USP_TXFIFO_THLD_MASK                    0x7c
	                                
	//USP_TXFIFO_LEVEL_CHK bit fields
	#define USP_TXFIFO_SC_MASK                      0x7
	#define USP_TXFIFO_LC_MASK                      0x1c00
	#define USP_TXFIFO_HC_MASK                      0x700000
	
	//USP_TXFIFO_OP bit fields
	#define USP_TXFIFO_RESET                        0x1             
	#define USP_TXFIFO_START                        0x2
	
	
	//USP_TXFIFO_STATUS bit fields
	#define USP_TXFIFO_LEVEL_MASK                   0x3f
	#define USP_TXFIFO_FULL                         0x20
	#define USP_TXFIFO_EMPTY                        0x40
	
	//USP_RX_DMA_IO_CTRL bit fields
	#define USP_RX_IO_MODE                          0x1
	#define USP_RX_FIFO_FLUSH			0x4
	
	//USP_RXFIFO_CTRL bit fields
	#define USP_RXFIFO_WIDTH_BYTE                   0x0
	#define USP_RXFIFO_WIDTH_WORD                   0x1
	#define USP_RXFIFO_WIDTH_DWORD                  0x2
	#define USP_RXFIFO_THLD_MASK                    0x7c
	                                
	//USP_RXFIFO_LEVEL_CHK bit fields
	#define USP_RXFIFO_SC_MASK                      0x7
	#define USP_RXFIFO_LC_MASK                      0x1c00
	#define USP_RXFIFO_HC_MASK                      0x700000
	
	//USP_RXFIFO_OP bit fields
	#define USP_RXFIFO_RESET                        0x1
	#define USP_RXFIFO_START                        0x2
	
	//USP_RXFIFO_STATUS bit fields
	#define USP_RXFIFO_LEVEL_MASK                   0x3f
	#define USP_RXFIFO_FULL                         0x20
	#define USP_RXFIFO_EMPTY                        0x40
#endif

//SIB_INT_ENABLE, SIB_INT_STATUS bit fields
#define SIB_INT_MASK_ALL                        0xff0000
#define SIB_INT_DMA_RX_MASK                     0x10000
#define SIB_INT_DMA_TX_MASK                     0x20000
#define SIB_INT_RX_FF_MASK                      0x40000
#define SIB_INT_TX_FE_MASK                      0x80000
#define SIB_INT_RX_OF_MASK                      0x100000
#define SIB_INT_TX_UF_MASK                      0x200000
#define SIB_INT_RX_THLD_MASK                    0x400000
#define SIB_INT_TX_THLD_MASK                    0x800000

//SIB_CTRL
#define SIB_AUD_SAMPLE_DIV_MASK                 0xff
#define SIB_TEL_SAMPLE_DIV_MASK                 0xff00
#define SIB_EXT_CLK_SEL                         0x10000
#define SIB_CLK_DIV_MASK                        0x60000
#define SIB_CHK_CNTR_TIMEOUT                    0x80000
#define SIB_LOOP_BACK_MODE                      0x100000
#define SIB_AUD_SEL_USPFIFO                     0x200000
#define USP3_SIB_MODE_SEL                       0x400000

//SIB_ENA
#define SIB_PORT_ENABLE                          0x1

//SIB_STATE_REG
#define SIB_RD_END_FLAG                          0x8
#define SIB_WT_END_FLAG                          0x4
#define SIB_AUDCODEC_ENA_FLAG                    0x2
#define SIB_TELCODEC_ENA_FLAG                    0x1

//USP DMA CHANNEL SELECT
#define USP0_2_CHN8				0x0
#define USP0_2_CHN9				0x0
#define USP0_2_CHN10				0x0
#define USP0_2_CHN11				0x0

#define USP1_2_CHN8				0x1
#define USP1_2_CHN9				(0x1<<3)
#define USP1_2_CHN10				(0x1<<6)
#define USP1_2_CHN11				(0x1<<9)

#define USP2_2_CHN8				0x2
#define USP2_2_CHN9				(0x2<<3)
#define USP2_2_CHN10				(0x2<<6)
#define USP2_2_CHN11				(0x2<<9)

#define USP3_2_CHN8				0x3
#define USP3_2_CHN9				(0x3<<3)
#define USP3_2_CHN10				(0x3<<6)
#define USP3_2_CHN11				(0x3<<9)

#define SIB_2_CHN8				0x4
#define SIB_2_CHN9				(0x4<<3)
#define SIB_2_CHN10				(0x4<<6)
#define SIB_2_CHN11				(0x4<<9)

#define USP4_2_CHN8				0x5
#define USP4_2_CHN9				(0x5<<3)
#define USP4_2_CHN10				(0x5<<6)
#define USP4_2_CHN11				(0x5<<9)

#define USP5_2_CHN8				0x6
#define USP5_2_CHN9				(0x6<<3)
#define USP5_2_CHN10				(0x6<<6)
#define USP5_2_CHN11				(0x6<<9)


//MODEL_SEL ADDRESS

#define	USP_MODEL_SEL		*((volatile unsigned *)0xffff5000)	
#define	USP_RESET_MODEL		*((volatile unsigned *)0xffff5010)	

	
//MODEL_SEL VALUE
#define	USP_CON_LOOP_BACK				0
#define	USP_CON_SPI_2401				1
#define	USP_CON_SPI_8536				2
#define	USP_CON_PBA313					3
#define	USP_CON_ASPORT					4
#define	USP_CON_BSPORT					5
#define	USP_CON_VSPORT					6
#define	USP_CON_AD73322					7
#define	USP_CON_USP_SCLK_INPUT				8
#define	USP_CON_USP_TXD_INPUT				9
#define	USP_CON_USP_RXD_INPUT				10
#define	USP_CON_USP_TFS_INPUT				11
#define	USP_CON_USP_RFS_INPUT				12
#define	USP_CON_UCB1200					13
#define	USP_CON_PCM					14
#define	USP_CON_IRDA_REVERSE				15


#endif//#ifndef _PALM2_USP_H_

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