📄 debug.h
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//
// Copyright (c) 2002 Palmmicro Communications Inc. All rights reserved.
//
// --------------------------------------------------------------------
/*++
Module Name:
debug.h
Abstract:
This file defines the header of the facilities for debugging.
Notes:
--*/
#ifndef _DEBUG_H_
#define _DEBUG_H_
#ifndef DONT_INCLUDE_DEBUG
#define MAX_STRING_LEN 256
#define DBG_BAUDRATE 38400
#if !defined (EXTERN_C)
#if !defined (__cplusplus)
#define EXTERN_C extern
#else
#define EXTERN_C extern "C"
#endif
#endif
EXTERN_C void _uart_init(int baudrate);
EXTERN_C void _usp5_init(int baudrate, int stop_bit_num, int irda_en, int irda_width,int irda_idle_level, int sample_div);
// write an output character to uart
EXTERN_C void _dbgputchar(char ch);
// write an output string to uart
EXTERN_C void _dbgputstring (const char *str);
// write an output hex number to uart
EXTERN_C void _dbgputhex (unsigned num);
// write an output decimal number to uart
EXTERN_C void _dbgputdec (unsigned num);
// get an input char from uart
EXTERN_C char _dbggetchar (void);
#define OEM_DEBUG_READ_NODATA 0x00
#ifndef VERILOG_SIM_MODE
// init the debug functions
#if !defined (DONT_USE_DEBUG_SERIAL)
#ifdef DEBUG_UART_PORT
#define DbgInit(baud) _uart_init ((int)(baud))
#else // DEBUG_UART_PORT
#define DbgInit(baud) _usp5_init ((int)(baud), 1, 0, 0, 0, 16)
#endif // DEBUG_UART_PORT
#else
#define DbgInit(baud)
#endif
void DbgPutChar(char ch);
void DbgPutString(const char *str);
void DbgPutHex(unsigned hex);
void DbgPutDec(unsigned dec);
char * DbgGetString(void);
void DbgFlush(void);
#else // #ifndef VERILOG_SIM_MODE
/*
The following definitions are for simulation purpose
Please be noted that only DbgPutChar, DbgPutString & DbgPutHex
are valid in simulation mode
*/
#define DbgInit(baud)
#define DbgPutChar(ch) sim_char(ch)
#define DbgPutHex(hex) sim_value_hex(hex)
#define DbgPutString(str) { char *pchar_for_sim = str; \
while (*pchar_for_sim) { \
sim_char(*pchar_for_sim); \
pchar_for_sim++; \
}\
}
#endif // #ifndef VERILOG_SIM_MODE
// define the simulation facilities
#define SimChar(x) sim_char(x)
#define SimStep(x) sim_step(x)
#define SimValue(x) sim_value(x)
#define SimStepHex(x) sim_step_hex(x)
#define SimValueHex(x) sim_value_hex(x)
#define SimCycleCount(x) sim_cycle_count(x)
#define SimMonitorOn() sim_monitor_on()
#define SimMonitorOff() sim_monitor_off()
#define SimSucceed() sim_succeed()
#define SimAbort() sim_abort()
#define LedErr(err) _lederr(err)
// define the behavior of DbgDelay() macro
#if defined(VERILOG_SIM_MODE) && defined(VERILOG_SIM_NODELAY)
#define DbgDelay(count)
#else
#define DbgDelay(count) { unsigned int __dbgcnt; for(__dbgcnt=0; __dbgcnt<count; __dbgcnt++);}
#endif
#endif // #ifndef DONT_INCLUDE_DEBUG
#if !defined (DEBUG_NBOOT)
#define TRACE(s)
#define WATCH(x)
#define CHECK_POINT()
#undef ASSERT
#define ASSERT(x)
#else /* !defined (DEBUG_NBOOT) */
#define TRACE(s) DbgPutString (s)
#define WATCH(x) \
do { DbgPutString ("\r\n" #x " = "); DbgPutHex (x); } while (0)
#define CHECK_POINT() do { \
DbgPutString ("\r\nCheck Point: file " __FILE__ "line "); \
DbgPutDec (__LINE__); \
} while (0)
#if !defined (ASSERT)
#define ASSERT(x) \
do { \
if (!(x)) { \
DbgPutString ("\r\n!!! assert failure: "#x); \
DbgPutString ("\r\n!!! file "__FILE__", line "); \
DbgPutDec (__LINE__); \
DbgPutString ("\r\n"); \
} \
} while (0)
#endif /* !defined (ASSERT) */
#endif /* !defined (DEBUG_NBOOT) */
#endif /* !defined (_DEBUG_H_) */
/* end of debug.h */
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