📄 opcodes.lst
字号:
Note:
This instruction calculate rounding ST toward zero
i.e. ignoring part righter that decimal .
Examples:
1.2 -> 1.0
-1.2 -> -1.0
3.0 -> 3.0
0.0 -> 0.0
1.5 -> 1.0
-2.0 -> -2.0
FPU Flags Affected: S,P,D,I,C1
FPU mode: Any
Physical Form: FRICHOP
COP (Code of Operation): DDH FCH
Clocks: Cx83D87 : 15
Cx83S87 : 15
CxEMC87 : 15
Cx487DLC :
---------------------------------------------------
OPCODE FRINEAR - FPU: Round to Integer Nearest method
FPU: Cyrix FPUs and 486s with FPU on chip
Type of Instruction: FPU instruction
Instruction: FRINEAR
Description:
ST <- ROUND ( ST,NEAREST )
Note:
This instruction calculate rounding ST toward nearest
Examples:
1.2 -> 1.0
-1.2 -> -1.0
3.0 -> 3.0
0.0 -> 0.0
1.5 -> 1.0
1.8 -> 2.0
-2.0 -> -2.0
FPU Flags Affected: S,P,D,I,C1
FPU mode: Any
Physical Form: FRINEAR
COP (Code of Operation): DFH FCH
Clocks: Cx83D87 : 15
Cx83S87 : 15
CxEMC87 : 15
Cx487DLC :
---------------------------------------------------
OPCODE FRINT2 - FPU: Round to Integer
FPU: Cyrix FPUs and 486s with FPU on chip
Type of Instruction: FPU instruction
Instruction: FRINT2
Description:
IF ( exact half ) THEN
{
ST <- SIGN(ST) * ROUND(ABS(ST)+0.5,NEAREST)
}
ELSE
{
ST <- ROUND ( ST,NEAREST )
}
END
Note:
This instruction calculate rounding ST toward nearest,
but if number is exact half then this instruction round
it toward signed infinity. Sign of this infinity is same
with sign of number.
Examples:
1.2 -> 1.0
-1.2 -> -1.0
3.0 -> 3.0
0.0 -> 0.0
1.5 -> 2.0
1.8 -> 2.0
-2.0 -> -2.0
-1.5 -> -2.0
FPU Flags Affected: S,P,D,I,C1
FPU mode: Any
Physical Form: FRINT2
COP (Code of Operation): DBH FCH
Clocks: Cx83D87 : 15
Cx83S87 : 15
CxEMC87 : 15
Cx487DLC :
---------------------------------------------------
OPCODE FRSTPM - FPU Reset Protected Mode
FPU: i287XL i287XLT
Type of Instruction: FPU instruction
Instruction: FRSTPM
Description:
Reset Cooprocessor from Protected Mode
to Real Address mode.
FPU Flags Affected: None
CPU mode:Any ???
Physical Form: FRSTPM
COP (Code of Operation): DBH E5H
Clocks: i287XL : 12
i287XLT : 12
---------------------------------------------------
OPCODE FSBP0 - FPU: Set Bank pointer to Bank # 0
FPU: IIT FPUs.
Type of Instruction: FPU instruction
Instruction: FSBP0
Description:
; This Instruction set current bank pointer to
; Bank # 0.
; Each bank contain eight 80bit registers
; There are 3 banks (0,1,2) in Chip
; After initialization FPU select bank # 0.
FPU Flags Affected: None
FPU mode: Any
Physical Form: FSBP0
COP (Code of Operation): DBH E8H
Clocks: IIT 2c87 : 6
IIT 3c87 : 6
IIT 3c87SX : 6
---------------------------------------------------
OPCODE FSBP1 - FPU: Set Bank pointer to Bank # 1
FPU: IIT FPUs.
Type of Instruction: FPU instruction
Instruction: FSBP1
Description:
; This Instruction set current bank pointer to
; Bank # 1.
; Each bank contain eight 80bit registers
; There are 3 banks (0,1,2) in Chip
; After initialization FPU select bank # 0.
FPU Flags Affected: None
FPU mode: Any
Physical Form: FSBP1
COP (Code of Operation): DBH EBH
Clocks: IIT 2c87 : 6
IIT 3c87 : 6
IIT 3c87SX : 6
---------------------------------------------------
OPCODE FSBP2 - FPU: Set Bank pointer to Bank # 2
FPU: IIT FPUs.
Type of Instruction: FPU instruction
Instruction: FSBP2
Description:
; This Instruction set current bank pointer to
; Bank # 2.
; Each bank contain eight 80bit registers
; There are 3 banks (0,1,2) in Chip
; After initialization FPU select bank # 0.
FPU Flags Affected: None
FPU mode: Any
Physical Form: FSBP2
COP (Code of Operation): DBH EAH
Clocks: IIT 2c87 : 6
IIT 3c87 : 6
IIT 3c87SX : 6
---------------------------------------------------
OPCODE FSETPM - FPU Set Protected Mode Adressing
FPU: 80287, i287XL i287XLT
Type of Instruction: FPU instruction
Instruction: FRSTPM
Description:
Setup Coprocessor for addressing in Protected mode
FPU Flags Affected: None
CPU mode:Any ???
Physical Form: FSETPM
COP (Code of Operation): DBH E4H
Clocks: i287XL : 12
i287XLT : 12
---------------------------------------------------
OPCODE FXRSTOR - Fast Restore F.P. Context
CPU: Katmai/Deschutes (IA MMX-2)
Type of Instruction: User
Instruction: FXRSTOR src
Description:
Fast Restore 94 (16-bit mode) or 108 (32-bit mode) byte of
F.P. context to memory.
Format of context as in standart x86 instruction: FSAVE.
Note: Check CPUID, EAX=1, bit 24 for knew CPU support this feature.
And then look at CR4.bit9.
Note: See FXSAVE for more information
Flags Affected: None
CPU mode: any
+++++++++++++++++++++++
Physical Form & COPs:
FXRSTOR mem512byte 0F AE mm001mmm
Clocks: n/a
---------------------------------------------------
OPCODE FXSAVE - Fast Save F.P. Context
CPU: Pentium II (Deschutes) +
Type of Instruction: User
Instruction: FXSAVE dest
Description:
Fast Save 94 (16-bit mode) or 108 (32-bit mode) byte of
F.P. context to memory.
Format of context as in standart x86 instruction: FSAVE.
Note: Check CPUID, EAX=1, bit 24 for knew CPU support this feature.
And then look at CR4.bit9.
Format of F.P./MMX Save Area:
Offset
(hex) Size Description
+00 WORD FCW (Control word)
+02 WORD FSW (Status word)
+04 WORD FTW (Tag word)
+06 WORD FOP (lower 11-bit F.P. opcode)
+08 DWORD IP (F.P. Instruction pointer)
+0C WORD CS
+10 DWORD DP (F.P. Data pointer)
+14 WORD DS
+18 DWORD MXCSR (Pentium III+)
see LDMXCSR instruction for more info
+20 TBYTE ST0/MM0
+30 TBYTE ST1/MM1
+40 TBYTE ST2/MM2
+50 TBYTE ST3/MM3
+60 TBYTE ST4/MM4
+70 TBYTE ST5/MM5
+80 TBYTE ST6/MM6
+90 TBYTE ST7/MM7
+A0 16BYTE XMM0 (Pentium III+)
+B0 16BYTE XMM1 (Pentium III+)
+C0 16BYTE XMM2 (Pentium III+)
+D0 16BYTE XMM3 (Pentium III+)
+E0 16BYTE XMM4 (Pentium III+)
+F0 16BYTE XMM5 (Pentium III+)
+100 16BYTE XMM6 (Pentium III+)
+110 16BYTE XMM7 (Pentium III+)
All other fields are reserved.
Full length of Save/Restore area is 512 byte. (200h)
Flags Affected: None
CPU mode: any
+++++++++++++++++++++++
Physical Form & COPs:
FXSAVE mem512byte 0F AE mm000mmm
Clocks: n/a
---------------------------------------------------
OPCODE IBTS - Insert Bits String
CPU: 80386 step A0-B0 only
Type of Instruction: User
Instruction: IBTS base,bitoffset,len,sorc
Description:
Write bit string length <len> bits from
<sorc> [bits <len> .. 0 ] (lowest bits) to bitfield,
defined by <base> and bitsoffset <bitoffset> from this base
to start of the field to write. String write from this start
field bit to higher memory addresses or register bits.
Flags Affected: None
CPU mode: RM,PM,VM
+++++++++++++++++++++++
Physical Form: IBTS r/m16,AX,CL,r16
IBTS r/m32,EAX,CL,r32
COP (Code of Operation) : 0FH A7H Postbyte
Clocks: IBTS
80386: 12/19
---------------------------------------------------
OPCODE ICEBP - PWI Mode BreakPoint, ICE address space
CPU: IBM 486SLC2
Type of Instruction: System
Instruction: ICEBP
Description:
IF (condition) THEN ; see condition below
{
SAVE STATUS OF EXECUTION TO ICE space;
ENTER SMM;
}
ELSE
{
INT 1;
}
END
Note: This condition can be set before execution this instruction:
CPL=0
MSR1000H.EPCEA=1
MSR1000H.EPWI=1
See Appendix X for more info.
Flags Affected: None
CPU mode: RM,PM0
Physical Form: ICEBP
COP (Code of Operation): F1H
Clocks: IBM 486SLC2 : 460
---------------------------------------------------
OPCODE ICEBP - In-Circuit Emulator Breakpoint
CPU: some models of i486, i386, Pentium, Pentium Pro
Type of Instruction: System
Instruction: ICEBP
Description:
IF (condition) THEN ; see condition below
{
CHANGED TO THE ICE instruction mode;
}
ELSE
{
INT 1;
}
END
Note: 386/486: Condition is DR7.bit12=1
(CPU must be supported ICE).
Note: This instruction very usefull to debbuging as Single-Byte Interrupt
but it generate never int 3, but int 1.
Note: On Pentium Interrupt redirection initiately disabled on PMCR
(Probe Mode Control Register), which is only accessable via debug port
i.e. Need external hardware for enable normal ICEBP execution.
Note: On Pentium Pro situation is the same.
But in Pentium Pro Intel named this instruction INT01.
Flags Affected: None
CPU mode: RM,PM0
Physical Form: ICEBP
COP (Code of Operation): F1H
Clocks: : N/A
---------------------------------------------------
OPCODE ICERET - Return from PWI mode, ICE space
CPU: IBM 486SLC2
Type of Instruction: System Operation
(Work only then CPL=0)
Instruction: ICERET
Description:
Load All Registers (Include Shadow Registers) from Table
Which Begin on place pointed ES:EDI, and return from PWI
mode.
Format of ICERET Table:
Offset Len Description
0H 4 CR0
4H 4 EFLAGS
8H 4 EIP
CH 4 EDI
10H 4 ESI
14H 4 EBP
18H 4 ESP
1CH 4 EBX
20H 4 EDX
24H 4 ESX
28H 4 EAX
2CH 4 DR6
30H 4 DR7
34H 4 TR (16 bit, zero filled up)
38H 4 LDT ---------
3CH 4 GS ---------
40H 4 FS ---------
44H 4 DS ---------
48H 4 SS ---------
4CH 4 CS ---------
50H 4 ES ---------
54H 4 TSS.attrib
58H 4 TSS.base
5CH 4 TSS.limit
60H 4 Reserved
64H 4 IDT.base
68H 4 IDT.limit
6CH 4 REP OUTS overrun flag
70H 4 GDT.base
74H 4 GDT.limit
78H 4 LDT.attrib
7CH 4 LDT.base
80H 4 LDT.limit
84H 4 GS.attrib
88H 4 GS.base
8CH 4 GS.limit
90H 4 FS.attrib
94H 4 FS.base
98H 4 FS.limit
9CH 4 DS.attrib
A0H 4 DS.base
A4H 4 DS.limit
A8H 4 SS.attrib
ACH 4 SS.base
B0H 4 SS.limit
B4H 4 CS.attrib
B8H 4 CS.base
BCH 4 CS.limit
C0H 4 ES.attrib
C4H 4 ES.base
C8H 4 ES.limit
Unknown Unusable area
;; Temporary registers:
100H 4 TST
104H 4 IDX
108H 4 TMPH
10CH 4 TMPG
110H 4 TMPF
114H 4 TMPE
118H 4 TMPD
11CH 4 TMPC
120H 4 TMPB
124H 4 TMPA
128H 4 CR2
12CH 4 CR3
130H 4 MSR1001H (31-0)
134H 4 MSR1001H (63-32)
138H 4 MSR1000H (15-0)
13CH 4 DR0
140H 4 DR1
144H 4 DR2
148H 4 DR3
14CH 4 PEIP
Length of table is 150H bytes.
see Appendix X for more info.
Note: For descriptor format refer to LOADALL and RES3 instructions.
Flags Affected: All (FLAGS Register Reload)
CPU mode: SMM
Physical Form: ICERET
COP (Code of Operation)⌨️ 快捷键说明
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