📄 opcodes.lst
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CVTSI2SS - Scalar Signed INT32 to Single-FP Conversion
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: CVTSI2SS dest,src
Description:
dest[<0>] <- (float) src[<0>];
<0> is 31..0
Physical Form and Timing:
CVTSI2SS xmm,r/m32 ---- F3 0F 2A /r ---- ??
-----------------------------------------------------------------
CVTSS2SI - Scalae Single-FP to Signed INT32 Conversion
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: CVTSS2SI dest,src
Description:
dest[<0>] <- (int) src[<0>];
src is in Single F.P. format
<0> is 31..0
Physical Form and Timing:
CVTSS2SI r32,xmm/m32 ---- F3 0F 2D /r ---- ??
-----------------------------------------------------------------
CVTTPS2PI - Packed Single-FP to Packed INT32 Conversion (Truncate)
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: CVTTPS2PI dest,src
Description:
dest[<0>] <- (int) src[<0>];
dest[<1>] <- (int) src[<1>];
<0> is 31..0
<1> is 63..32
Physical Form and Timing:
CVTTPS2PI mm,xmm/m64 ---- 0F 2C /r ---- ??
-----------------------------------------------------------------
CVTTSS2SI - Scalar Single-FP to Signed INT32 Conversion (Truncate)
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: CVTTSS2SI dest,src
Description:
dest[<0>] <- (int) src[<0>]
if conversion is unexact returning truncate value,
if result > maximal 32-bit value, result will be 0x80000000
Physical Form and Timing:
CVTTSS2SI r32,xmm/m32 ---- F3 0F 2C /r ---- ??
-----------------------------------------------------------------
DIVPS - Packed Single-FP Divide
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: DIVPS dest,src
Description:
dest[<0>] = dest[<0>] / src[<0>];
dest[<1>] = dest[<1>] / src[<1>];
dest[<2>] = dest[<2>] / src[<2>];
dest[<3>] = dest[<3>] / src[<3>];
Physical Form and Timing:
DIVPS xmm1,xmm2/m128 ---- 0F 5E /r ---- 24-106
-----------------------------------------------------------------
DIVSS - Scalar Single-FP. Divide
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: DIVSS dest,src
Description:
dest[<0>] = dest[<0>] / src[<0>];
Physical Form and Timing:
DIVSS xmm1,xmm2/r32 ---- F3 0F 5E /r ---- 7-??
---------------------------------------------------
OPCODE EMMS - Empty MMX State
CPU: all which supported IA MMX:
Pentium (P55C only), Pentium (tm) Pro (P6) future models
Type of Instruction: User
Instruction: EMMS
Description:
FloatPointTagWord <- FFFFh
Note: The EMMS instruction sets the values of the floating-point (FP) tag
word to empty (all ones). EMMS marks the registers as available, so
they can subsequently be used by floating-point instructions.
If a floating-point instruction loads into one of the registers
before it has been reset by the EMMS instruction, a floating-point
stack overflow can occur, which results in a FP exception or incorrect
result. All other MMX instructions validate the entire FP tag word (all
zeros).
This instruction must be used to dear the MMX state at the end of all
MMX routines, and before calling other routines that may execute
floating-point instructions.
Flags affected: None
Exceptions:
RM PM VM SMM Description
#UD #UD #UD #UD If CR0.EM = 1
#NM #NM #NM #NM If CR0.TS = 1
#MF #MF #MF #MF If pending FPU Exception
++++++++++++++++++++++++++++++++++++++
COP & Times:
EMMS 0FH 77H
P55C: n/a
future P6: n/a
---------------------------------------------------
OPCODE ESC - Escape Extrnal Cooprocessors
CPU: 8086...80386, any Hybrid 486.
Type of Instruction: User
Instruction: ESC Number,R/M
Description: This Instruction uses for Link with External Coprocessors
Such as NPX. External Coprocessors look at command sequence
at get ESC. CPU give Memory Operand sending to A-bus EA
doing pseudo-read operation.
{ If 2nd Operand is Register then Do Nothing,
If 2nd Operand is Memory then set EA (Effective Address)
in Address Bus }
First operand is Part of Command that Ext. coprocessors get.
Flags Affected: None
Example: ESC 0Fh,DX means FSQRT
Note: ESC mnemonic was used for 8086 CPU, later all were used alternative
mnemonic for cooprocessor instructions, such as FSQRT.
CPU mode: RM,PM,VM,SMM
+++++++++++++++++++++++
Physical Form:
COP (Code of Operation) : <1101 1xxx> Postbyte
Clocks: ESC n,Reg ESC n,Mem8/Mem16
8088: 2 8/12+EA
286: 9-20 9-20
386: N/A N/A
486: N/A N/A
---------------------------------------------------
OPCODE EXT - Extract Bit Field
CPU: NEC/Sony all V-series
Type of Instruction: User
Instruction: EXT start,len
Description:
AX <- BitField [
BASE = DS:SI
START BIT OFFSET = start
LENGTH = len
];
Note: si and start automatically UPDATE
Flags Affected: None
CPU mode: RM
+++++++++++++++++++++++
Physical Form : EXT reg8,reg8
COP (Code of Operation) : 0FH 33H PostByte
Clocks: EXT reg8,reg8
NEC V20: 26-55
---------------------------------------------------
OPCODE F4X4 - FPU: Multiplicate vector on Matrix 4x4
FPU: IIT FPUs.
Type of Instruction: FPU instruction
Instruction: F4X4
Description:
; This Instruction Multiplicate vector on
; Matrix 4X4
_ _ _ _ _ _
| | | | | |
| Xn | | A00 A01 A02 A03 | | X0 |
| Yn | = | A10 A11 A12 A13 | X | Y0 |
| Zn | | A20 A21 A22 A23 | | Z0 |
| Wn | | A30 A31 A31 A33 | | W0 |
|_ _| |_ _| |_ _|
; Data fetches/stores from/to FPU registers:
# of F E T C H E S STORE
Register Bank0 Bank1 Bank2 Bank0
ST X0 A33 A31 Xn
ST(1) Y0 A23 A21 Yn
ST(2) Z0 A13 A11 Zn
ST(3) W0 A03 A01 Wn
ST(4) A32 A30
ST(5) A22 A20
ST(6) A12 A10
ST(7) A02 A00
Note: See FSBP0,FSBP1,FSBP2 for more information
FPU Flags Affected: S
FPU mode: Any
Physical Form: F4X4
COP (Code of Operation): DBH F1H
Clocks: IIT 2c87 : 242
IIT 3c87 : 242
IIT 3c87SX : 242
---------------------------------------------------
OPCODE FCMOVcc - Floating Point Conditional Move
CPU: P6
Type of Instruction: User
Instruction: FCMOVcc dest,sorc
Description:
IF condition(cc) is true THEN dest <- sorc;
Flags Affected: Int: None
Fp : None
Note: Testing Integer flags:
cc Meaning Test Flags Description
B Below CF=1 <
NB Not Below CF=0 >=
E Equal ZF=1 =
NE Not Equal ZF=0 !=
BE Below Equal (CF=1 .OR. ZF=1) <=
NBE Not BelowEqual (CF=0 .AND. ZF=0) >
U Unordered PF=1
NU Not Unordered PF!=1
CPU mode: RM,PM,VM,SMM
+++++++++++++++++++++++
Physical Form & COPs:
FCMOVB ST,STi DA C0+i
FCMOVE ST,STi DA C8+i
FCMOVBE ST,STi DA D0+i
FCMOVU ST,STi DA D8+i
FCMOVNB ST,STi DB C0+i
FCMOVNE ST,STi DB C8+i
FCMOVNBE ST,STi DB D0+i
FCMOVNU ST,STi DB D8+i
Clocks: N/A
---------------------------------------------------
OPCODE FCOMI - Floating Point Compare setting Integer Flags
CPU: P6
Type of Instruction: User
Instruction: FuCOMIp ST0,STi
Description:
CASE ( result (compare(ST0,STi) ) OF
{ ; ZF PF CF
Not Comparable: 1 1 1
ST0 > STi : 0 0 0
ST0 < STi : 0 0 1
ST0 = STi : 1 0 0
}
CASE ( FP_stack_status ) OF
{ ; SF
Overflow : 1
Underflow : 0
Otherwize : 0
}
CASE ( instruction ) OF
{
FCOMI,FUCOMI : No FP stack adjustment;
FCOMIP,FUCOMIP : POP ST;
}
Flags Affected: Int: CF,ZF,PF,SF
Fp : None
Note: In any case Sign of zero Ignored , so +0.0 = -0.0
CPU mode: RM,PM,VM,SMM
+++++++++++++++++++++++
Physical Form & COPs:
FCOMI ST0,STi DB F0+i
FCOMIP ST0,STi DF F0+i
FUCOMI ST0,STi DB E8+i
FUCOMIP ST0,STi DF E8+i
Clocks: N/A
-----------------------------------------------
OPCODE FEMMS - Faster Enter/Exit of MMX of F.P. state
CPU: AMD-3D
Type of Instruction: User
Instruction: FEMMS (no operands)
Description:
Clear MMX state after MMX instructions.
(FPU.TAG <- FFFFh).
Faster version of EMMS.
Flags Affected: None
++++++++++++++++++++++++++++++++++
COP & Times:
FEMMS 0FH 0EH
---------------------------------------------------
OPCODE FINT - Finished Interrupt
CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
Type of Instruction: System
Instruction: FINT
Description:
Inticate to Internal Interrupt controller that
interrupt service Routine is completed. (EOI)
Flags Affected: None
CPU mode: RM
+++++++++++++++++++++++
Physical Form: FINT
COP (Code of Operation) : 0Fh 92h
Clocks: 2
---------------------------------------------------
OPCODE FNDISI - Disable NPX Interrupt
FPU: i8087 only
Type of Instruction: FPU instruction
Instruction: FNDISI
Description:
CW.IEM <- 1; // Enable NPX interrupt
Note: IEM is 7 of FPU.CW
FPU Flags Affected: None
CPU mode: 8087 support just real mode
Physical Form: FNDISI
COP (Code of Operation): DBH E1H
Clocks: i8087 5
---------------------------------------------------
OPCODE FNENI - Enable NPX Interrupt
FPU: i8087 only
Type of Instruction: FPU instruction
Instruction: FNENI
Description:
CW.IEM <- 0; // Enable NPX interrupt
Note: IEM is 7 of FPU.CW
FPU Flags Affected: None
CPU mode: 8087 support just real mode
Physical Form: FNENI
COP (Code of Operation): DBH E0H
Clocks: i8087 5
---------------------------------------------------
OPCODE FNSTDW - FPU Not wait Store Device Word register
FPU: i387SL Mobile
Type of Instruction: FPU instruction
Instruction: FNSTDW dest
Description:
dest <- Device Word
Format of Device word:
bit(s) Description
0-7 Reserved
8 S - Status bit:
if S=1 then FP device is a static design and OS
or APM Bios may set CLK slow to 0 Mhz without
lost any data.
9-15 Reserved
Note: Device word register valid only after FNINIT
FPU Flags Affected: None
CPU mode: Any
Physical Form: FNSTDW AX
COP (Code of Operation): DFH E1H
Clocks: i387SL Mobile: 13
---------------------------------------------------
OPCODE FNSTSG - FPU Not wait Store Signature Word register
FPU: i387SL Mobile
Type of Instruction: FPU instruction
Instruction: FNSTSG dest
Description:
dest <- Signature Word
Format of Signature word:
bit(s) Description
3-0 Revision
7-4 Steppin
11-8 Family
15-12 Version
Note:
For i387(tm) SL Mobile Signature is:
Version = 2
Family = 3 ; 387
Stepping = 1 ; Ax step
Revision = 0 ; x0 step
i.e i387(tm) SL is A0 step
Note: This FPU is out of life
Note: Signature word register valid only after FNINIT
FPU Flags Affected: None
CPU mode: Any
Physical Form: FNSTSG AX
COP (Code of Operation): DFH E2H
Clocks: i387SL Mobile: 13
---------------------------------------------------
OPCODE FPO2 - Floating Point Operations 2nd Way
CPU: NEC/Sony all V-series
Type of Instruction: User
Instruction: FPO2 fp_op,mem
Description:
This instruction was building for sending FP commands to
NEC NPX which never be realized
Flags Affected: None
CPU mode: RM
+++++++++++++++++++++++
Physical Form : FPO2 imm4,reg/mem
COP (Code of Operation) :
If imm4 in range 0-7 then
66H mmFFFMMM there FFF is imm4.
If imm4 in range 7-F then
67H mmFFFMMM there FFF is imm4.
Clocks: FPO2 imm4,reg/mem
NEC V20: 2/11
---------------------------------------------------
OPCODE FRICHOP - FPU: Round to Integer chop method
FPU: Cyrix FPUs and 486s with FPU on chip
Type of Instruction: FPU instruction
Instruction: FRICHOP
Description:
ST <- ROUND ( ST,CHOP )
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