📄 opcodes.lst
字号:
Register XAM aliased with port # FF80h indicated current mode
of operation.
Format of XAM register (READ ONLY):
15..1 reserved
0 XA Flag, if=1 then in XA mode.
Format of V53 PSW:
15..12 1
11 V
10 DIR
9 IE
8 BRK
7 S
6 Z
5 0
4 AC
3 0
2 P
1 1
0 CY
Flags Affected: None
CPU mode: RM
+++++++++++++++++++++++
Physical Form: BRKXA imm8
COP (Code of Operation) : 0Fh E0h imm8
Clocks: 12
---------------------------------------------------
OPCODE BSWAP - Bytes Swap
CPU: I486 +
Type of Instruction: User
Instruction: BSWAP dwordr
Description:
XCHG BYTE dwordr[31:24],dwordr[7:0]
XCHG BYTE dwordr[23:16],dwordr[15:8]
; Need Good Picture to Show It
Notes: This instruction used for converting big-endian
(Intel) format to little-endian (Motorolla etc.) format.
Flags Affected: None
CPU mode: RM,PM,VM,SMM
Physical Form: BSWAP r32
COP (Code of Operation): 0FH 11001rrr (For 32bit segment)
Clocks: Cyrix Cx486SLC : 4
i486 : 1
Pentium : 1
Cyrix Cx486DX : 4
UMC U5S : 2
IBM 486BL3X : 9
---------------------------------------------------
OPCODE BTCLR - Bit Test, If it True Clear and Branch
CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
Type of Instruction: User
Instruction: BTCLR var,bitnumber,Short_Label
Description:
IF BIT(bitnumber OF var) =1 THEN
{
PC <- PC + ext - disp8;
BIT(bitnumber OF var) <-0
}
Flags Affected: None
CPU mode: RM
+++++++++++++++++++++++
Physical Form: BTCLR reg/mem8,imm3, short_label
COP (Code of Operation) : 0Fh 9Ch PostByte imm3 Short_Label (Total=5 bytes)
Clocks: 29
---------------------------------------------------
OPCODE CALLN - Call Native Mode Routine
CPU: NEC/Sony V20/V30 etc
Type of Instruction: System
Instruction: CALLN intnum
Description:
CALLN instruction call (interrupt service in Native Mode)
from 8080 emulation mode:
PUSH FLAGS
PUSH CS
PUSH IP
IF <- 0
TF <- 0
MD <- 1
MOV CS,0:[intnum*4+2]
MOV IP,0:[intnum*4]
Flags Affected: IF,TF,MD
CPU mode: 8080 Emulation
+++++++++++++++++++++++
Physical Form: CALLN imm8
COP (Code of Operation) : EDH EDH imm8
Clocks:
NEC V20/V30: 38-58
---------------------------------------------------
OPCODE CLEAR1 - Clear one bit
CPU: NEC/Sony all V-series.
Type of Instruction: User
Instruction: CLEAR1 dest,bitnumb
Description:
BIT bitnumb OF dest <- 0;
Flags Affected: None
CPU mode: RM
+++++++++++++++++++++++
Physical Form: CLEAR1 reg/mem8,CL
COP (Code of Operation) : 0FH 12H Postbyte
Physical Form: CLEAR1 reg/mem8,imm8
COP (Code of Operation) : 0FH 1AH Postbyte imm8
Physical Form: CLEAR1 reg/mem16,CL
COP (Code of Operation) : 0FH 13H Postbyte
Physical Form: CLEAR1 reg/mem16,imm8
COP (Code of Operation) : 0FH 1BH Postbyte imm8
Clocks: CLEAR1
r/m8,CL r/m8,i8 r/m16,CL r/m16,i8
NEC V20: 5/14 6/15 5/14 6/15
---------------------------------------------------
OPCODE CMOVcc - Conditional Move
CPU: P6
Type of Instruction: User
Instruction: CMOVcc dest,sorc
Description:
IF condition(cc) is true THEN dest <- sorc;
Flags Affected: None
CPU mode: RM,PM,VM,SMM
+++++++++++++++++++++++
Physical Form & COPs:
CMOVO reg,reg/mem 0FH 40H Postbyte
CMOVNO reg,reg/mem 0FH 41H Postbyte
CMOVC reg,reg/mem 0FH 42H Postbyte
CMOVNC reg,reg/mem 0FH 43H Postbyte
CMOVZ reg,reg/mem 0FH 44H Postbyte
CMOVNZ reg,reg/mem 0FH 45H Postbyte
CMOVNA reg,reg/mem 0FH 46H Postbyte
CMOVA reg,reg/mem 0FH 47H Postbyte
CMOVS reg,reg/mem 0FH 48H Postbyte
CMOVNS reg,reg/mem 0FH 49H Postbyte
CMOVP reg,reg/mem 0FH 4AH Postbyte
CMOVNP reg,reg/mem 0FH 4BH Postbyte
CMOVL reg,reg/mem 0FH 4CH Postbyte
CMOVNL reg,reg/mem 0FH 4DH Postbyte
CMOVNG reg,reg/mem 0FH 4EH Postbyte
CMOVG reg,reg/mem 0FH 4FH Postbyte
Clocks: ~1 (~pairing with other instructions)
---------------------------------------------------
OPCODE CMP4S - Compare for packed BCD strings
CPU: NEC/Sony all V-series
Type of Instruction: User
Instruction: CMP4S
Description:
SetFlaGS( BCD STRING (ADDRESS=ES:DI,LENGTH=CL) -
BCD STRING (ADDRESS=DS:SI,LENGTH=CL) );
Note: si,di, other registers not changed
Flags Affected: OF,CF,ZF
;; ZF set if RESULT of subtraction is zero.
;; CF,OF set as result of operation with most
;; signification BCDs.
CPU mode: RM
+++++++++++++++++++++++
Physical Form: CMP4S
COP (Code of Operation) : 0FH 26H
Clocks: CMP4S
NEC V20: ~7+19*CL
-----------------------------------------------------------------
CMPPS - Packed Single FP-Compare
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: CMPPS dest,src,predicate
Description:
operation predicate
EQ equal (dest == src) 0
LT less-than (dest < src) 1
LE less-equal (dest <= src) 2
UNORD unordered (dest ? src) 3
NEQ not-equal (dest <> src) 4
NLT not-less-that (dest => src) 5
NLE not-less-equal (dest > src) 6
ORD ordered !(dest ? src) 7
par for i = 0 to 3 do
cmp<i> = dest[<i>] operation(predicate) src[<i>];
if cmp<i> = true then
dest[<i>] = 0xffffffff;
else
dest[<i>] = 0x00000000;
endif
endfor endpar
<0> = 31..0 <2> = 95..64
<1> = 63..32 <3> = 127..96
Note: Compilers may implement additional instructions:
CMPEQPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,0
CMPLTPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,1
CMPLEPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,2
CMPUNORDPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,3
CMPNEQPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,4
CMPNLTPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,5
CMPNLEPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,6
CMPORDPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,7
Physical Form and Timing:
CMPPS xmm1,xmm2/m128,imm8 ---- 0F C2 /r imm8 ---- 1-2
-----------------------------------------------------------------
CMPSS - Scalar Single FP-Compare
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: CMPSS dest,src,predicate
Description:
operation predicate
EQ equal (dest == src) 0
LT less-than (dest < src) 1
LE less-equal (dest <= src) 2
UNORD unordered (dest ? src) 3
NEQ not-equal (dest <> src) 4
NLT not-less-that (dest => src) 5
NLE not-less-equal (dest > src) 6
ORD ordered !(dest ? src) 7
cmp = dest[<0>] operation(predicate) src[<0>];
if cmp = true then
dest[<0>] = 0xffffffff;
else
dest[<0>] = 0x00000000;
endif
<0> = 31..0 <2> = 95..64
<1> = 63..32 <3> = 127..96
Note: Compilers may implement additional instructions:
CMPEQSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,0
CMPLTSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,1
CMPLESS xmm1,xmm2 <=> CMPSS xmm1,xmm2,2
CMPUNORDSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,3
CMPNEQSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,4
CMPNLTSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,5
CMPNLESS xmm1,xmm2 <=> CMPSS xmm1,xmm2,6
CMPORDSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,7
Physical Form and Timing:
CMPSS xmm1,xmm2/m128,imm8 ---- F3 0F C2 /r imm8 ---- 1-2
---------------------------------------------------
OPCODE CMPXCHG8B - Compare and exchange 8 bytes
CPU: Pentium (tm), Pentium Pro(tm), AMD Am5k86
Type of Instruction: Operation
Instruction: CMPXCHG8B dest
Note: dest is memory operand: QWORD PTR [memory]
Description:
IF ( QWORD(EDX:EAX) = dest) THEN
{
ZF <- 1;
dest <- QWORD(ECX:EBX);
}
ELSE
{
ZF <- 0;
EDX:EAX <- dest
}
END
Flags Affected: ZF
CPU mode: RM,PM,VM,SMM
Physical Form: CMPXCHG8B mem64
COP (Code of Operation) : 0FH C7H Postbyte
Clocks: Pentium : 10
Note: Postbyte MMRRRMMM: MM<>11 if (==) then INT 6
---------------------------------------------------
OPCODE CMPXCHG - Compare and exchange
CPU: i486+
Type of Instruction: User
Instruction: CMPXCHG dest,sorc
Description:
Acc = if OperationSize(8) -> AL
OperationSize(16) -> AX
OperationSize(32) -> EAX
IF ( Acc = dest) THEN
{
ZF <- 1;
dest <- sorc;
}
ELSE
{
ZF <- 0;
Acc <- dest;
}
END
Note: This instruction used to support semaphores
Flags Affected: ZF ( see description)
OF,SF,AF,PF,CF ( like CMP instruction ) ( see description)
CPU mode: RM,PM,VM,SMM
+++++++++++++++++++++++
Physical Form: CMPXCHG r/m8,r8
COP (Code of Operation) : 0FH A6H Postbyte ; i486 (A-B0 step)
: 0FH B0H Postbyte ; i486 (B1+ step clones
; and upgrades)
Clocks:
Intel i486 : 6/7 if compare OK
: 6/10 if compare FAIL
Cyrix Cx486SLC : 5/7
Pentium (tm) : 6
Penalty if cache miss :
Intel i486 : 2
Cyrix Cx486SLC : 1
+++++++++++++++++++++
Physical Form: CMPXCHG r/m16,r16
CMPXCHG r/m32,r32
COP (Code of Operation) : 0FH A7H Postbyte ; i486 (A-B0 step)
: 0FH B1H Postbyte ; i486 (B1+ step clones
; and upgrades)
Clocks:
Intel i486 : 6/7 if compare OK
: 6/10 if compare FAIL
Cyrix Cx486SLC : 5/7
Pentium (tm) : 6
Penalty if cache miss :
Intel i486 : 2
Cyrix Cx486SLC : 1
-----------------------------------------------------------------
COMISS - Scalar Ordered Single-FP Compare and Set EFLAGS
CPU: Pentium III+ (KNI/MMX2)
Type of instruction: User
Instruction: COMISS dest,src
Description:
OF <- 0;
SF <- 0;
AF <- 0;
if (dest[<0>] UNORD src[<0>]) then
ZF <- 1;
PF <- 1;
CF <- 1;
elif (dest[<0>] > src[<0>]) then
ZF <- 0;
PF <- 0;
CF <- 0;
elif (dest[<0>] < src[<0>]) then
ZF <- 0;
PF <- 0;
CF <- 1;
else
ZF <- 1;
PF <- 0;
CF <- 0;
endif
<0> is 31..0
Physical Form and Timing:
COMISS xmm1,xmm2/m32 ---- 0F 2F /r ---- ?
---------------------------------------------------
OPCODE CPUID - CPU Identification
CPU: Intel 486DX/SX/DX2 SL Enhanced and all later
Intel processors include ( IntelDX4, IntelSX2,
Pentium etc.), UMC microprocessors: U5S,U5SD,U5S-VL.
Cyrix M1, AMD K5, Intel P6, and AMD Ehnanced Am486 CPU,
such as A80486DX4-100SV8B.
Note: i.e. 1993+ years processors produced by Intel
Note: To know if your CPU support CPUID instruction
try to set ID flag ( bit 21 of EFLAGS ) to 1, and
if it sets this mean that CPUID support.(Soft).
Or If Your CPU is Intel Look for '&E' signature on
Top side of Chip.(Hard)
Type of Instruction: Operation
Instruction: CPUID
Description:
IF (EAX=0) THEN // All
{
EAX <- Maximum value of EAX to CALL CPUID instruction
1 for all processors (date 1 September 1994)
may be >1 in future microprocessors
;; EBX,EDX and ECX contain a OEM name string
;; for Intel this string is 'GenuineIntel'
EBX <- 756E6547H i.e. 'Genu'
EDX <- 49656E69H i.e. 'ineI'
ECX <- 6C65746EH i.e. 'ntel'
;; for UMC this string is 'UMC UMC UMC '
EBX <- 20434D55H i.e. 'UMC '
EDX <- 20434D55H i.e. 'UMC '
ECX <- 20434D55H i.e. 'UMC '
;; for Cyrix this string is 'CyrixInstead' (Cx6x86,Cx5x86 steps B+)
;; for AMD this string is 'AuthenticAMD' (K6,K5,486 Enhanced CPUs)
;; for last NexGen is 'NexGenDriven' (Nx5x86 latest models)
;; for Centaur Technology is 'CentaurHauls' (IDT)
;; for Rise Technology is 'RiseRiseRise'
}
ELSEIF (EAX=1) THEN // All
{
EAX[3:0] <- Stepping ID
EAX[7:4] <- Model
EAX[11:8] <- Family
; 3 - 386 family
; 4 - i486 family
; 5 - Pentium family
; 6 - Pentium Pro family
EAX[15:12] <- Reserved
; 0 - Original OEM processor
; 1 - OverDrive
; 2 - Dual Processor
Note: Pentium P54C have pin CPUTYPE which
define is this CPU First or Second e.t.c
in System.
So, if this chip set in "First" socket it
return for example 0425h, but THIS chip
return 2425h if we insert it in "Second"
socket.
Note: Refer to Appendix B for more information.
EAX[31:16] <- Reserved and set to 0s now
Note: This value in EAX[31:0] is upper 32-bit of 96-bit processor
serial number.
EDX <- Compability flags
;; below all info if bit flag =1
EDX[0] <- FPU: FPU on Chip
EDX[1] <- VME: Virtual Mode Extention present
EDX[2] <- DE: Debbuging Extentions
EDX[3] <- PSE: CPU support 4MB size pages
EDX[4] <- TSC: TSC present (See RDTSC command)
EDX[5] <- MSR: CPU have Pentium Compatible MSRs
EDX[6] <- PAE: Physical Address Extension (Intel)
EDX[6] <- PTE: Support PTE (Cyrix)
When set in PTE TLB will not be flushed
when CR3 is written.
EDX[7] <- MCE: Machine Check exception
EDX[8] <- CX8: Support CMPXCHG8B instruction
EDX[9] <- APIC: Local APIC on Chip (Intel)
PGE: Page Global Extension (K5)
EDX[10]<- reserved
EDX[11]<- SEP: Fast System Call feature (Pentium Pro)
EDX[12]<- MTRR: CPU support Memory Type Range Register (MTRR)
EDX[13]<- PGE: Page Global Feature support
EDX[14]<- MCA: Machine Check Architecture
EDX[15]<- CMOV: CPU support CMOV instruction
EDX[16]<- PAT: Page Attribute Table
EDX[17]<- PSE36: CPU support 4MB Pages for access memory higher
that 2GB.
EDX[18]<- SN: CPU Support Processor Serial Number
EDX[22..19] <- Reserved
EDX[23] <- MMX: CPU support IA MMX
EDX[24] <- FXSR: CPU Support Fast Save/Restore (IA MMX-2)
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