msr.lst

A Programmer s Reference to BIOS, DOS, and Third-Party Calls

	unit mask: 00h = from MMX to FP, 01h = from FP to MMX
 CDh	(P-II) SIMD assists (EMMS instructions executed)
 CEh	(P-II) MMX instructions retired
 CFh	(P-II) saturated arithmetic instructions retired
 D0h	decoded instructions
 D1h	documented as unused
 D2h	partial stall cycles or events
 D3h	documented as unused
 D4h	(P-II) segment rename stalls
	set unit mask to sum of: 01h for ES, 02h for DS, 04h for FS, 08h for GS
 D5h	(P-II) segment renames (unit mask as for D4h)
 D6h	(P-II) retired segment renames
 D7h-DFh	documented as unused
 E0h	decoded branch instructinos
 E1h	documented as unused
 E2h	BTB misses
 E3h	documented as unused
 E4h	bogus branches (predictions generated for non-branch instructions)
 E5h	documented as unused
 E6h	number of times BACLEAR asserted (number of static branch predictions)
 E7h-FFh	documented as unused
SeeAlso: #R0047
----------S00000187--------------------------
MSR 00000187h - Pentium Pro - "EVNTSEL1" - PERFORM. COUNTER EVENT SELECTION 1
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 000000C2h,MSR 00000186h,#R0047,MSR 00000011h,MSR 00000013h,#R0047
----------S000001D3--------------------------
MSR 000001D3h - Pentium Pro - ???
----------S000001D9--------------------------
MSR 000001D9h - Pentium Pro, PentiumII - "DEBUGCTLMSR" DEBUGGING CONTROL
Size:	16 bits

Bitfields for Pentium Pro Debugging Control MSR:
Bit(s)	Description	(Table R0049)
 63-16	reserved
 15	enable execution trace messages
 14	enable execution trace messages
 13-7	reserved
 6	enable execution trace messages
 5	performance monitor/Breakpoint pins
 4	performance monitor/Breakpoint pins
 3	performance monitor/Breakpoint pins
 2	performance monitor/Breakpoint pins
 1	Branch Trap Flag
 0	enable Last Branch records (see MSR 000001DBh,MSR 000001DCh)
----------S000001DB--------------------------
MSR 000001DBh - Pentium Pro, PentiumII - "LASTBRANCHFROMIP"
Desc:	stores the address from which a branch was last taken
SeeAlso: MSR 000001DCh,MSR 000001DDh
----------S000001DC--------------------------
MSR 000001DCh - Pentium Pro, PentiumII - "LASTBRANCHTOIP"
Desc:	stores the destination address of the last taken branch instruction
SeeAlso: MSR 000001DBh,MSR 000001DEh
----------S000001DD--------------------------
MSR 000001DDh - Pentium Pro, PentiumII - "LASTINTFROMIP"
Desc:	stores the address at which an interrupt last occurred
SeeAlso: MSR 000001DBh,MSR 000001DEh
----------S000001DE--------------------------
MSR 000001DEh - Pentium Pro, PentiumII - "LASTINTTOIP"
Desc:	stores the address to which the last interrupt caused a branch
SeeAlso: MSR 000001DCh,MSR 000001DDh
----------S000001E0--------------------------
MSR 000001E0h - Pentium Pro - "ROB_CR_BKUPTMPDR6"
Size:	>= 3 bits

Bitfields for Pentium Pro MSR 000001E0h:
Bit(s)	Description	(Table R0050)
 63-3	???
 2	Fast String Enable (default is enabled)
 1-0	reserved
Note:	if bit 2 is set, REP MOVS moves 64 bits each clock cycle if both source
	  and target are QWORD-aligned
----------S00000200--------------------------
MSR 00000200h - Pentium Pro - "MTRRphysBase0"
SeeAlso: MSR 000000FEh,MSR 00000201h,MSR 00000202h
----------S00000201--------------------------
MSR 00000201h - Pentium Pro - "MTRRphysMask0"
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000202h
----------S00000202--------------------------
MSR 00000202h - Pentium Pro - "MTRRphysBase1"
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000203h
----------S00000203--------------------------
MSR 00000203h - Pentium Pro - "MTRRphysMask1"
SeeAlso: MSR 000000FEh,MSR 00000201h,MSR 00000202h
----------S00000204--------------------------
MSR 00000204h - Pentium Pro - "MTRRphysBase2"
----------S00000205--------------------------
MSR 00000205h - Pentium Pro - "MTRRphysMask2"
----------S00000206--------------------------
MSR 00000206h - Pentium Pro - "MTRRphysBase3"
----------S00000207--------------------------
MSR 00000207h - Pentium Pro - "MTRRphysMask3"
----------S00000208--------------------------
MSR 00000208h - Pentium Pro - "MTRRphysBase4"
----------S00000209--------------------------
MSR 00000209h - Pentium Pro - "MTRRphysMask4"
----------S0000020A--------------------------
MSR 0000020Ah - Pentium Pro - "MTRRphysBase5"
----------S0000020B--------------------------
MSR 0000020Bh - Pentium Pro - "MTRRphysMask5"
----------S0000020C--------------------------
MSR 0000020Ch - Pentium Pro - "MTRRphysBase6"
----------S0000020D--------------------------
MSR 0000020Dh - Pentium Pro - "MTRRphysMask6"
----------S0000020E--------------------------
MSR 0000020Eh - Pentium Pro - "MTRRphysBase7"
----------S0000020F--------------------------
MSR 0000020Fh - Pentium Pro - "MTRRphysMask7"
----------S00000250--------------------------
MSR 00000250h - Pentium Pro - "MTRRfix64K_00000"
Desc:	control the 64K region from 00000h to 0FFFFh
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000258h
----------S00000258--------------------------
MSR 00000258h - Pentium Pro - "MTRRfix16K_80000"
Desc:	control the 16K region from 80000h to 83FFFh
SeeAlso: MSR 000000FEh,MSR 00000250h,MSR 00000259h
----------S00000259--------------------------
MSR 00000259h - Pentium Pro - "MTRRfix16K_A0000"
Desc:	control the 16K region from A0000h to A3FFFh
----------S00000268--------------------------
MSR 00000268h - Pentium Pro - "MTRRfix4K_C0000"
Desc:	control the 4K region from C0000h to C0FFFh
----------S00000269--------------------------
MSR 00000269h - Pentium Pro - "MTRRfix4K_C8000"
Desc:	control the 4K region from C8000h to C8FFFh
----------S0000026A--------------------------
MSR 0000026Ah - Pentium Pro - "MTRRfix4K_D0000"
Desc:	control the 4K region from D0000h to D0FFFh
----------S0000026B--------------------------
MSR 0000026Bh - Pentium Pro - "MTRRfix4K_D8000"
Desc:	control the 64K region from D8000h to D8FFFh
----------S0000026C--------------------------
MSR 0000026Ch - Pentium Pro - "MTRRfix4K_E0000"
Desc:	control the 64K region from E0000h to E0FFFh
----------S0000026D--------------------------
MSR 0000026Dh - Pentium Pro - "MTRRfix4K_E8000"
Desc:	control the 64K region from E8000h to E8FFFh
----------S0000026E--------------------------
MSR 0000026Eh - Pentium Pro - "MTRRfix4K_F0000"
Desc:	control the 64K region from F0000h to F0FFFh
----------S0000026F--------------------------
MSR 0000026Fh - Pentium Pro - "MTRRfix4K_F8000"
Desc:	control the 64K region from F8000h to F8FFFh
----------S00000277--------------------------
MSR 00000277h - PentiumII - Page Attribute Table
Note:	see CPUID instruction for PAT support
----------S00000280--------------------------
MSR 00000280h - PentiumII - ???
----------S000002FF--------------------------
MSR 000002FFh - Pentium Pro - "MTRRdefType" - DEFAULT MEMORY TYPE
Note:	this MSR sets the memory type to use for any range not claimed by one
	  of the other MTRRs
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000250h

Bitfields for Pentium Pro MSR 000002FFh:
Bit(s)	Description	(Table R0051)
 63-12	reserved
 11	"MTRRenable" enable Memory Type Register registers
 10	Fixed MTRR enable
 9-3	reserved
 2-0	default memory type
----------S00000400--------------------------
MSR 00000400h - Pentium Pro - "MC0_CTL" Machine Check Control 0
SeeAlso: MSR 00000401h,MSR 00000402h,MSR 00000404h,MSR 0000410h
----------S00000401--------------------------
MSR 00000401h - Pentium Pro - "MC0_STATUS" Machine Check Status 0
SeeAlso: MSR 00000400h,MSR 00000403h

Bitfields for Pentium Pro Machine Check Status:
Bit(s)	Description	(Table R0052)
 63	"MC_STATUS_V"
 62	"MC_STATUS_O"
 61	"MC_STATUS_UC"
 60	"MC_STATUS_EN"
 59	"MC_STATUS_MISCV"
 58	"MC_STATUS_ADDRV"
 57	"MC_STATUS_DAM"
 56-32	reserved
 31-16	"MC_STAT_MSCOD"
 15-0	"MC_STAT_MACCOD"
----------S00000402--------------------------
MSR 00000402h - Pentium Pro - "MC0_ADDR" Machine Check Address 0
SeeAlso: MSR 00000400h,MSR 00000403h
----------S00000403--------------------------
MSR 00000403h - Pentium Pro - "MC0_MISC"
SeeAlso: MSR 00000401h,MSR 00000402h
----------S00000404--------------------------
MSR 00000404h - Pentium Pro - "MC1_CTL" Machine Check Control 1
SeeAlso: MSR 00000400h,MSR 00000408h
----------S00000405--------------------------
MSR 00000405h - Pentium Pro - "MC1_STATUS" Machine Check Status 1
----------S00000406--------------------------
MSR 00000406h - Pentium Pro - "MC1_ADDR" Machine Check Address 1
----------S00000407--------------------------
MSR 00000407h - Pentium Pro - "MC1_MISC"
----------S00000408--------------------------
MSR 00000408h - Pentium Pro - "MC2_CTL" Machine Check Control 2
SeeAlso: MSR 00000400h,MSR 00000404h,MSR 0000040Ch
----------S00000409--------------------------
MSR 00000409h - Pentium Pro - "MC2_STATUS" Machine Check Status 2
----------S0000040A--------------------------
MSR 0000040Ah - Pentium Pro - "MC2_ADDR" Machine Check Address 2
----------S0000040B--------------------------
MSR 0000040Bh - Pentium Pro - "MC2_MISC"
----------S0000040C--------------------------
MSR 0000040Ch - Pentium II - "MC4_CTL" Machine Check Control 4
SeeAlso: MSR 000040Dh,MSR 00000400h,MSR 00000404h,MSR 00000408h
----------S0000040D--------------------------
MSR 0000040Dh - Pentium II - "MC4_STATUS" Machine Check Status 4
SeeAlso: MSR 000040Ch,MSR 000040Eh
----------S0000040E--------------------------
MSR 0000040Eh - Pentium II - "MC4_ADDR" Machine Check Address 4
SeeAlso: MSR 000040Ch,MSR 000040Dh
----------S00000410--------------------------
MSR 00000410h - Pentium Pro - "MC3_CTL" Machine Check Control 3
SeeAlso: MSR 00000400h,MSR 00000404h,MSR 0000040Ch
----------S00000411--------------------------
MSR 00000411h - Pentium Pro - "MC3_STATUS" Machine Check Status 3
----------S00000412--------------------------
MSR 00000412h - Pentium Pro - "MC3_ADDR" Machine Check Address 3
----------S00000413--------------------------
MSR 00000413h - Pentium Pro - "MC3_MISC"
----------S00001000--------------------------
MSR 00001000h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER
Size:	19 bits
Access:	Read/Write
SeeAlso: MSR 00001001h,MSR 00001002h

Bitfields for IBM 386/486 SLC Processor Operation Register:
Bit(s)	Description	(Table R0053)
 63-19	reserved
 18	(486SLC only) Low Power PLA
 17	(486SLC only) Bus Read
 16	(486SLC only) Cache Parity Generate Error
 15	enable cacheability of NPX operands
 14	enable PWI ADS
 13	enable Low Power Halt Mode (HLT instruction stops CPU clock)
 12	extended Out instruction (CPU waits for READY after any output)
 11	cache reload bit
 10	enable internal KEN# signal
 9	disable cache lock mode
 8	reserved
 7	enable cache
 6	enable DBCS
 5	enable Power Interrupt
 4	enable Flush Snooping
 3	enable Snoop Input
 2	address line A20 mask (see also #02753,#P0415)
 1	enable cache parity checking
 0	Cache Parity Error occurred
SeeAlso: #R0054,#R0055
----------S00001000--------------------------
MSR 00001000h - Pentium Pro - DEBUG REGISTER 0 
SeeAlso: MSR 00001001h"Pro",MSR 00001007h"Pro"
----------S00001001--------------------------
MSR 00001001h - IBM 386/486 SLC - CACHE REGION CONTROL REGISTER
Size:	48 bits
SeeAlso: MSR 00001000h,MSR 00001002h

Bitfields for IBM 386/486 SLC Cache Region Control Register:
Bit(s)	Description	(Table R0054)
 63-48	reserved
 47-32	extended memory cache memory limit (number of 64K blocks above 1M
	  which may be cached)
 31-16	first megabyte read-only flags (each bit represents 64K)
 15-0	first megabyte cacheable flags (each bit represents 64K)
SeeAlso: #R0053,#R0055
----------S00001001--------------------------
MSR 00001001h - Pentium Pro - DEBUG REGISTER 1
SeeAlso: MSR 00001000h"Pro",MSR 00001002h"Pro"
----------S00001002--------------------------
MSR 00001002h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER
Size:	30 bits
SeeAlso: MSR 00001000h,MSR 00001001h,MSR 00001004h

Bitfields for IBM 386/486 SLC Processor Operation Register:
Bit(s)	Description	(Table R0055)
 63-30	reserved
 29	enable External Dynamic Frequency Shift
 28	Dynamic Frequency Shift ready
 27	Dynamic Frequency Shift Mode
 26-24	clocking mode
	000 clock x1
	011 clock doubler
	100 clock tripler
 23-0	reserved
SeeAlso: #R0053,#R0054
----------S00001002--------------------------
MSR 00001002h - Pentium Pro - DEBUG REGISTER 2
SeeAlso: MSR 00001001h"Pro",MSR 00001003h"Pro"
----------S00001003--------------------------
MSR 00001003h - Pentium Pro - DEBUG REGISTER 3
SeeAlso: MSR 00001002h"Pro",MSR 00001004h"Pro"
----------S00001004--------------------------
MSR 00001004h - IBM 486BL3 - PROCESSOR CONTROL REGISTER
Size:	24 bits
SeeAlso: MSR 00001000h

Bitfields for IBM 486BL3 Processor Control Register:
Bit(s)	Description	(Table R0056)
 63-24	reserved
 23	OS/2 boot (0=DD1 hardware, 1=DD0 hardware)
 22	MOV CR0,x Decode
	0: DD0, DD1A, DD1B, DD1D hardware
	1: DD1C hardware
 21	reserved
 20	Cache Low Power (DD1 only: cache disabled when not in use)
 19	reserved
 18	NOP timing
	0: 2 cycles on DD0, 3 cycles on DD1
	1: 3 cycles on DD0, 2 cycles on DD1
 17	bus pipelining for 16-bit accesses
 16-5	reserved???
 4	MOVS split
 3	power-saving cache feature
 2	reserved
 1	enable MOV CRx decode
	(reserved on DD1B, DD1C)
 0	reserved
SeeAlso: MSR 00001000h
----------S00001004--------------------------
MSR 00001004h - Pentium Pro - DEBUG REGISTER 4 
SeeAlso: MSR 00001003h"Pro",MSR 00001005h"Pro"
----------S00001005--------------------------
MSR 00001005h - Pentium Pro - DEBUG REGISTER 5 
SeeAlso: MSR 00001004h"Pro",MSR 00001006h"Pro"
----------S00001006--------------------------
MSR 00001006h - Pentium Pro - DEBUG REGISTER 6 
SeeAlso: MSR 00001005h"Pro",MSR 00001007h"Pro"
----------S00001007--------------------------
MSR 00001007h - Pentium Pro - DEBUG REGISTER 7 
SeeAlso: MSR 00001006h"Pro",MSR 00001000h"Pro",MSR 00002000h"Pro"
----------S00002000--------------------------
MSR 00002000h - Pentium Pro/II - CONTROL REGISTER 0
SeeAlso: MSR 00001000h"Pro",MSR 00002002h"Pro"
----------S00002002--------------------------
MSR 00002002h - Pentium Pro/II - CONTROL REGISTER 2
SeeAlso: MSR 00002000h"Pro",MSR 00002003h"Pro"
----------S00002003--------------------------
MSR 00002003h - Pentium Pro/II - CONTROL REGISTER 3
SeeAlso: MSR 00002002h"Pro",MSR 00002004h"Pro"
----------S00002004--------------------------
MSR 00002004h - Pentium Pro/II - CONTROL REGISTER 4
SeeAlso: MSR 00002003h"Pro",MSR 00002000h"Pro"
----------S80000000--------------------------
MSR 80000000h - Pentium - M