msr.lst

A Programmer s Reference to BIOS, DOS, and Third-Party Calls

Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000115h,MSR 00000117h"Centaur",#R0041
----------S00000117--------------------------
MSR 00000117h - Centaur (IDT) C6/WinChip2 - Memory Configuration Register #7
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000110h,MSR 00000116h"Centaur",#R0041
----------S00000118--------------------------
MSR 00000118h - PentiumII - "BBL_CR_DECC" READ/WRITE L2 CACHE ECC BITS
Size:	8 bits
SeeAlso: MSR 00000088h,MSR 00000116h"PentiumII",MSR 00000119h
----------S00000119--------------------------
MSR 00000119h - PentiumII - "BBL_CR_CTL" - CACHE CONTROL REGISTER
SeeAlso: MSR 00000118h,MSR 0000011Ah

Bitfields for PentiumII "BBL_CR_CTL":
Bit(s)	Description	(Table R0043)
 63-22	reserved
 21	disable processor serial number (Pentium III)
 20-19	reserved
 18	use supplied ECC
 17	reserved
 16	L2 hit
 15-14	reserved
 13-12	state from L2 entry
	00 invalid
	01 shared
	10 exclusive
	11 modified
 11-10	way number from L2 cache
 9-8	way number to L2
 7	reserved
 6-5	state to L2 entry (as for bits 13-12)
 4-0	L2 command
	00010 read L2 control register
	00011 write L2 control register
	010mm tag write with data read
	01100 data read with LRU update
	01110 tag read with data read
	01111 tag inquire
	100mm tag write
	111mm tag write w/ data write
	('mm' = MESI state, coded as for bits 13-12)
----------S0000011A--------------------------
MSR 0000011Ah - PentiumII - "BBL_CR_TRIG" TRIGGER CACHE CONFIGURATION CYCLE
Note:	a write (must write 00000000h!) to this MSR triggers a cache
	  configuration access cycle
SeeAlso: MSR 00000088h,MSR 00000118h,MSR 0000011Bh
----------S0000011B--------------------------
MSR 0000011Bh - PentiumII - "BBL_CR_BUSY" CHECK IF CACHE CONFIG IN PROGRESS
Size:	1 bit
Access:	Read-Only
Note:	if bit 0 is set, an L2 cache configuration access command is in
	  progress
SeeAlso: MSR 00000088h,MSR 00000118h,MSR 0000011Ah
----------S0000011E--------------------------
MSR 0000011Eh - Pentium II - "BBL_CR_CTL3" L2 CACHE CONTROL REGISTER 3
SeeAlso: MSR 00000088h,MSR 00000116h,MSR 0000011Ah,MSR 0000011Bh

Bitfields for Pentium II L2 cache control:
Bit(s)	Description	(Table R0044)
 63-26	reserved
 25	(read-only) cache bus fraction
 24	reserved
 23	(read-only) L2 hardware disable
 22-20	supported L2 physical address range
	000  512M
	001    1G
	010    2G
	011    4G
	100    8G
	101   16G
	110   32G
	111   64G
 19	reserved
 18	enable cache state error checking
 17-13	cache size per bank
	00001 256K
	00010 512K
	00100	1M
	01000	2M
	10000	4M
 12-11	(read-only) number of L2 banks
 10-9	(read-only) L2 associativity
	00 direct-mapped
	01 2-way associative
	10 4-way associative
	11 reserved
 8	L2 cache enabled
 7	CRTN parity checking enabled
 6	address parity checking enabled
 5	enable ECC testing of L2 cache memory
 4-1	L2 cache latency
 0	L2 has been configured
----------S00000120--------------------------
MSR 00000120h - Centaur (IDT) C6/WinChip2 - Memory Config Register Control
Size: 25 bits
Access:	Write-Only on C6, Read-Write on WinChip2
SeeAlso: MSR 00000107h,MSR 00000110h,MSR 00000117h

Bitfields for Centaur (IDT) C6/WinChip2 Memory Configuration Control Register:
Bit(s)	Description	(Table R0045)
 63-25	reserved
 24-20	reserved (1)
---WinChip2---
 19-17	Trait Mode Key (must write this value to bits 8-6 to enable MCRs)
 16	MCR7 is in use
 15	MCR6 is in use
 14	MCR5 is in use
 13	MCR4 is in use
 12	MCR3 is in use
 11	MCR2 is in use
 10	MCR1 is in use
 9	MCR0 is in use
 8-6	Trait Mode Control (memory config registers enabled if these bits equal
	  bits 19-17)
---C6---
 19-6	reserved
------
 5	reserved
 4	enable weak write ordering
 3-2	write merging for string writes
	00 forward combining
	01 forward/overlapped
	10 forward/reverse
	11 forward/reverse/overlap
 1-0	write merging for non-stack/non-string writes
	00 forward combining
	01 forward/overlapped
	10 forward/reverse
	11 forward/reverse/overlap
SeeAlso: #R0041
----------S00000131--------------------------
MSR 00000131h - Pentium Pro - ???
SeeAlso: MSR 0000014Eh"Pentium"
----------S00000131--------------------------
MSR 00000131h - IDT WinChip2 - ???
SeeAlso: MSR 00000142h"IDT"
----------S00000142--------------------------
MSR 00000142h - IDT WinChip2 - ???
SeeAlso: MSR 00000131h"IDT",MSR 00000143h"IDT"
----------S00000143--------------------------
MSR 00000143h - IDT WinChip2 - ???
SeeAlso: MSR 00000142h"IDT",MSR 00000144h"IDT"
----------S00000144--------------------------
MSR 00000144h - IDT WinChip2 - ???
SeeAlso: MSR 00000143h"IDT",MSR 00000145h"IDT"
----------S00000145--------------------------
MSR 00000145h - IDT WinChip2 - ???
SeeAlso: MSR 00000144h"IDT",MSR 00000147h"IDT"
----------S00000147--------------------------
MSR 00000147h - IDT WinChip2 - ???
SeeAlso: MSR 00000145h"IDT",MSR 00000150h"IDT"
----------S0000014E--------------------------
MSR 0000014Eh - Pentium Pro - ???
----------S0000014F--------------------------
MSR 0000014Fh - Pentium Pro - ???
----------S00000150--------------------------
MSR 00000150h - Pentium Pro - ???
SeeAlso: MSR 0000014Fh"Pentium",MSR 00000151h"Pentium"
----------S00000150--------------------------
MSR 00000150h - IDT WinChip2 - ???
SeeAlso: MSR 00000147h"IDT",MSR 00000151h"IDT"
----------S00000151--------------------------
MSR 00000151h - Pentium Pro - ???
SeeAlso: MSR 00000150h"Pentium",MSR 00000154h"Pentium"
----------S00000151--------------------------
MSR 00000151h - IDT WinChip2 - ???
SeeAlso: MSR 00000131h"IDT",MSR 00000150h"IDT"
----------S00000154--------------------------
MSR 00000154h - Pentium Pro - ???
----------S0000015B--------------------------
MSR 0000015Bh - Pentium Pro - ???
----------S0000015F--------------------------
MSR 0000015Fh - Pentium Pro - ???
----------S00000174--------------------------
MSR 00000174h - Pentium II - "SYSENTER_CS" - SYSENTER target CS
Desc:	specify the 4GB flat-model Ring0 CS selector to which the SYSENTER
	  instruction will transfer control
Notes:	Intel has promised that this MSR will remain at this address in all
	  x86 processors supporting SYSENTER
	the SYSEXIT instruction will set CS to 16 more than the value in
	  this MSR and SS to 24 more than this MSR's value
	the SYSENTER and SYSEXIT instructions will raise a #GP(0) exception if
	  this MSR contains the value zero
SeeAlso: MSR 00000175h,MSR 00000176h
----------S00000175--------------------------
MSR 00000175h - Pentium II - "SYSENTER_ESP" - SYSENTER target ESP
Desc:	specify the Ring 0 ESP to be loaded by the SYSENTER instruction
Notes:	Intel has promised that this MSR will remain at this address in all
	  x86 processors supporting SYSENTER
	SYSENTER will set SS to a value 8 greater than that in SYSENTER_CS
SeeAlso: MSR 00000174h,MSR 00000176h
----------S00000176--------------------------
MSR 00000176h - Pentium II - "SYSENTER_EIP" - SYSENTER target EIP
Desc:	specify the 4GB flat-model offset to which the SYSENTER instruction
	  will transfer control
Note:	Intel has promised that this MSR will remain at this address in all
	  x86 processors supporting SYSENTER
SeeAlso: MSR 00000174h,MSR 00000175h
----------S00000179--------------------------
MSR 00000179h - Pentium Pro - "MCG_CAP" MACHINE CHECK GLOBAL CAPABILITY
Desc:	indicate how many banks of error-reporting MSRs are implemented
InstallCheck:	CPUID feature bit 14 is set
SeeAlso: MSR 0000017Ah,MSR 0000017Bh

Bitfields for Pentium Pro "MCG_CAP" register:
Bit(s)	Description	(Table R0046)
 63-8	unused???
 7-0	number of MCRs
----------S0000017A--------------------------
MSR 0000017Ah - Pentium Pro/II - "MCG_STATUS"
SeeAlso: MSR 00000179h,MSR 0000017Bh,INT 12"CPU"
----------S0000017B--------------------------
MSR 0000017Bh - Pentium Pro - "MCG_CTL"
SeeAlso: MSR 00000179h,MSR 0000017Ah
----------S00000186--------------------------
MSR 00000186h - Pentium Pro - "EVNTSEL0" - PERFORM. COUNTER EVENT SELECTION 0
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 000000C1h,MSR 00000187h,MSR 00000011h,MSR 00000012h

Bitfields for Pentium Pro Event Selection MSR:
Bit(s)	Description	(Table R0047)
 31-24	CMASK (counter mask)
	compare actual count for event on this clock cycle with mask; only
	  increment counter if count >= mask (count < mask if bit 23 set)
 23	invert result of CMASK condition
 22	enable counting of events
 21	reserved
 20	signal performance counter overflows via APIC input
 19	signal performance counter overflows via BP0/BP1 pin
 18	count occurrences, not duration
 17	OS (enable counting in ring 0)
 16	USER (enable counting in rings 1,2,3)
 15-8	UMASK (Unit Mask register; set to 0 to enable all count options)
 7-0	event type (see #R0048)

(Table R0048)
Values for Pentium Pro/Pentium II performance event type:
 00h-01h	documented as unused
 02h	number of store buffer forwards
 03h	number of store buffer blocks
 04h	number of store buffer drain cycles
 05h	misaligned data memory references
 06h	segment register loads
 07h-0Fh	documented as unused
 10h	executed computational FP operations
 11h	number of microcode-handled FP exceptions
 12h	number of multiplies
 13h	number of divisions
 14h	divider busy cycles
 15h-20h	documented as unused
 21h	L2 address strobes
 22h	L2 cache data bus wait cycles
 23h	L2 cache data bus transfer cycles
 24h	allocated L2-cache lines
 25h	allocated L2 modified lines
 26h	removed L2 lines
 27h	removed modified L2 lines
 28h	instruction fetches from L2 cache
 29h	loads requested from L2 cache
 2Ah	stores into L2 cache
 2Bh-2Dh	documented as unused
 2Eh	total L2 requests
 2Fh-3Fh	documented as unused
 40h	L1 Data Cache Unit load rquests
 41h	L1 DCU store requests
 42h	L1 DCU locked requests
 43h	total memory references (all types, reads+writes+internal retries)
 44h	documented as unused
 45h	L1 allocated lines
 46h	L1 allocated M-state lines
 47h	L1 evicted M-state lines
 48h	L1 outstanding miss cycles (weighted)
 49h	L1 data TLB misses
 4Ah-51h	documented as unused
 52h	(P-II) self-modifying code occurrences
 53h-5Fh	documented as unused
 60h	outstanding bus requests
 61h	number of cycles BNR pin driven
 62h	DRDY# asserted cycles
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 63h	number of cycles with LOCK asserted
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 64h	CPU receiving data cycles
 65h	burst-read transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 66h	read for ownership transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 67h	write-back transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 68h	instruction-fetch transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 69h	invalidate transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Ah	partial-write transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Bh	partial transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Ch	I/O transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Dh	deferred transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Eh	burst transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Fh	memory transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 70h	total of all transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 71h-78h	documented as unused
 79h	processor not-halted cycles
 7Ah	cycles in which HIT pin is driven
 7Bh	cycles in which HITM pin is driven
 7Ch-7Dh	documented as unused
 7Eh	bus-snoop stall cycles
 7Fh	documented as unused
 80h	instruction fetches
 81h	instruction fetch misses
 82h-84h	documented as unused
 85h	L1 instruction TLB misses
 86h	instruction-fetch stall cycles
 87h	instruction-length decoder stall cycles
 88h-A1h	documented as unused
 A2h	resource-related stall cycles
 A3h-AFh	documented as unused
 B0h	(P-II) MMX instructions executed
 B1h	(P-II) saturated arithmetic instructions executed
 B2h	(P-II) MMX uOPs executed on Port #0--3
 B3h	(P-II) MMX instructions
	unit mask selects type(s): 01h packed multiply, 02h packed shift,
	  04h pack operations, 08h unpack operations, 10h packed logical,
	  20h packed arithmetic
 B4h-BFh	documented as unused
 C0h	retired instructions
 C1h	retired FLOPs
 C2h	retired uOPs
 C3h	documented as unused
 C4h	retired branch predictions
 C5h	retired mispredicted branches
 C6h	total cycles with interrupts disabled
 C7h	total cycles with interrupts disabled and interrupt(s) pending
 C8h	received hardware interrupts
 C9h	retired taken branches
 CAh	retired taken mispredicted branches
 CBh	documented as unused
 CCh	(P-II) transitions between FP and MMX states