msr.lst

A Programmer s Reference to BIOS, DOS, and Third-Party Calls

 E1h	data cache (linear tag) (see #R0025)
 E4h	code cache (instruction) (see #R0026)
 E5h	code cache (linear tag) (see #R0027)
 E6h	code cache (valid bits) (see #R0028)
 E7h	code cache (branch-prediction bits) (see #R0029)
 E8h	4K TLB (page) (see #R0030)
 E9h	4K TLB (linear tag) (see #R0031)
 EAh	4M TLB (page) (see #R0032)
 EBh	4M TLB (linear tag) (see #R0033)
 ECh	data cache (physical tag) (see #R0034)
 EDh	code cache (physical tag) (see #R0035)
SeeAlso: #R0023

Bitfields for AMD AmK586 data cache linear tag:
Bit(s)	Description	(Table R0025)
 31-26	reserved (0)
 25	cache line is dirty
 24	user/supervisor
 23	read/write
 22	0
 21	linear address valid
 20-0	tag
SeeAlso: #R0024,#R0034

Bitfields for AMD Am5k86 code cache instruction:
Bit(s)	Description	(Table R0026)
 31-26	reserved (0)
 25	start bit 1
 24	end bit 1
 23	opcode bit 1
 22-21	map (ROPs/MROM) 1
 20-13	byte 1
 12	start bit 0
 11	end bit 0
 10	opcode bit 0
 9-8	map (ROPs/MROM) 0
 7-0	byte 0
SeeAlso: #R0024,#R0027,#R0035

Bitfields for Am5k86 code cache linear tag:
Bit(s)	Description	(Table R0027)
 31-20	reserved (0)
 19-0	bits 31-12 of linear address
SeeAlso: #R0024,#R0026,#R0028,#R0035

Bitfields for Am5k86 code cache valid bits:
Bit(s)	Description	(Table R0028)
 31-18	reserved (0)
 17	linear tag is valid
 16	user/supervisor
 15-0	bitmask of valid bytes
SeeAlso: #R0024,#R0026,#R0035

Bitfields for Am5k86 code cache branch prediction bits:
Bit(s)	Description	(Table R0029)
 31-19	reserved (0)
 18	predicted branch taken
 17-14	offset of last byte of predicted branch instruction within block
 13-12	predicted target column
 11-4	predicted target index
 3-0	target byte
SeeAlso: #R0024

Bitfields for Am5k86 4K TLB page:
Bit(s)	Description	(Table R0030)
 31-22	reserved (0)
 21	page cache disable
 20	page write-through
 19-0	page frame address
SeeAlso: #R0024,#R0031,#R0032

Bitfields for Am5k86 4K TLB linear tag:
Bit(s)	Description	(Table R0031)
 31-20	reserved (0)
 19	global valid bit
 18	TLB entry is dirty
 17	user/supervisor
 16	read/write
 15	entry is valid
 14-0	tag (bits 31-17 of address)
SeeAlso: #R0024,#R0030,#R0033

Bitfields for Am5k86 4M TLB page:
Bit(s)	Description	(Table R0032)
 31-12	reserved (0)
 11	page cache disable
 10	page write-through
 9-0	page frame address
SeeAlso: #R0024,#R0030,#R0033

Bitfields for Am5k86 4M TLB linear tag:
Bit(s)	Description	(Table R0033)
 31-15	reserved (0)
 14	global valid bit
 13	TLB entry is dirty
 12	user/supervisor
 11	read/write
 10	entry is valid
 9-0	tag (bits 31-22 of address)
SeeAlso: #R0024,#R0031,#R0032

Bitfields for Am5k86 data cache physical tag:
Bit(s)	Description	(Table R0034)
 31-23	reserved (0)
 22-21	MESI status
	00 invalid
	01 shared
	10 modified
	11 exclusive
 20-0	tag (bits 31-11 of physical address)
SeeAlso: #R0024,#R0035

Bitfields for Am5k86 code cache physical tag:
Bit(s)	Description	(Table R0035)
 31-21	reserved (0)
 20	valid
 19-0	tag (bits 31-12 of physical address)
SeeAlso: #R0024,#R0034
----------S00000083--------------------------
MSR 00000083h - AMD Am5k86 (AMD-K5) - HARDWARE CONFIGURATION REGISTER
Size:	8 bits
SeeAlso: MSR 00000082h

Bitfields for AMD Am5k86 (AMD-K5) Hardware Configuration Register:
Bit(s)	Description	(Table R0036)
 63-8	reserved
 7	disable data cache
 6	disable instruction cache
 5	disable branch prediction
 4	enable write allocation (stepping 4 and higher only)
 3-1	debug control
	000 off
	001 enable branch trace (requires bit 5 set as well)
	100 enable Probe Mode on debug trap
	other reserved
 0	disable Stopping Processor Clock in Halt and Stop Grant states
SeeAlso: #R0023
----------S00000085--------------------------
MSR 00000085h - AMD-K5 - WRITE ALLOCATE TOP-OF-MEMORY AND CONTROL REGISTER
Note:	this MSR is supported on K5 models 1/2/3 stepping 4 and higher only
	For more information about MSRs 85h and 86h refer to "Implementation
	  of Write Allocate in the K86(tm) Processors", application note,
	  order# 21326, http://www.amd.com
SeeAlso: MSR 00000086h
	!!!amd\21062e.pdf p.95
----------S00000086--------------------------
MSR 00000086h - AMD-K5 - WRITE ALLOCATE PROGRAMMABLE MEMORY RANGE REGISTER
Note:	this MSR is supported on K5 models 1/2/3 stepping 4 and higher only
SeeAlso: MSR 00000085h
----------S00000088--------------------------
MSR 00000088h - Pentium Pro, PentiumII - "BBL_CR_D0" CHUNK 0 DATA REGISTER
Note:	this register is used to read from and write to L2 cache
SeeAlso: MSR 00000089h,MSR 0000008Ah,MSR 00000116h
----------S00000089--------------------------
MSR 00000089h - Pentium Pro, PentiumII - "BBL_CR_D1" CHUNK 1 DATA REGISTER
Note:	this register is used to read from and write to L2 cache
SeeAlso: MSR 00000088h,MSR 0000008Ah,MSR 00000116h
----------S0000008A--------------------------
MSR 0000008Ah - Pentium Pro, PentiumII - "BBL_CR_D2" CHUNK 2 DATA REGISTER
Note:	this register is used to read from and write to L2 cache
SeeAlso: MSR 00000088h,MSR 00000089h,MSR 00000116h
----------S0000008B--------------------------
MSR 0000008Bh - Pentium Pro - "BIOS_SIGN" BIOS UPDATE SIGNATURE
Size:	64 bits
Access:	Read/Write
Desc:	used to determine which (if any) microcode update has been loaded into
	  the CPU
Notes:	whenever a microcode update is loaded, the PentiumPro modifies the
	  operation of the CPUID instruction to store both the standard CPUID
	  model information and a 32-bit microcode update ID into this MSR; if
	  no microcode update has been loaded, the MSR remains unchanged
	  (it is normally cleared to 0 before using CPUID to test for updates)
	the low 32 bits of this register (if modified by CPUID) contains the
	  standard model/stepping information, while the high 32 bits contain
	  the microcode update ID
SeeAlso: MSR 00000079h
----------S0000008B--------------------------
MSR 0000008Bh - PentiumII - "BBL_CR_D3" CHUNK 3 DATA REGISTER
Notes:	this register is used to read from and write to L2 cache
	whether this MSR is the BIOS update signature or L2 data depends on
	  the usage model
SeeAlso: MSR 00000088h,MSR 00000089h,MSR 00000116h
----------S000000AE--------------------------
MSR 000000AEh - Pentium Pro - ???
----------S000000C1--------------------------
MSR 000000C1h - Pentium Pro - "PERFCTR0" PERFORMANCE COUNTER REGISTER 0
Note:	the performance measure counted by this MSR is set through MSR 0186h
SeeAlso: MSR 000000C2h,MSR 00000012h,MSR 00000186h
----------S000000C2--------------------------
MSR 000000C2h - Pentium Pro - "PERFCTR1" PERFORMANCE COUNTER REGISTER 1
Note:	the performance measure counted by this MSR is set through MSR 0187h
SeeAlso: MSR 000000C1h,MSR 00000013h,MSR 00000187h
----------S000000FE--------------------------
MSR 000000FEh - Pentium Pro - "MTRRcap" MEMORY TYPE RANGE REGISTER CAPABILITIES
Desc:	determine how many and what type of Memory Type Range Registers are
	  implemented
SeeAlso: MSR 00000200h,MSR 00000250h,MSR 000002FFh

Bitfields for Pentium Pro "MTRRcap" register:
Bit(s)	Description	(Table R0037)
 63-8	???
 7-0	number of Memory Type Range Registers (at MSR 02xxh)
----------S00000107--------------------------
MSR 00000107h - Centaur (IDT) WinChip C6/WinChip2 - Feature Control Register #1
Size:	30 bits
SeeAlso: MSR 00000108h,MSR 00000109h

Bitfields for Centaur (IDT) C6/WinChip2 Feature Control Register #1:
Bit(s)	Description	(Table R0038)
 61-31	reserved
 30	enable MOV TRx instructions
 29	disable CPUID instruction
 28	don't use alternative "divide 5 by 2" EFLAGS
	0 = use Centaur (IDT) flags
	1 = use Intel flags
 27-26	reserved
 25-22	stepping ID
 21	reserved
 20	enable AMD 3DNow! instructions (WinChip2)
 19	enable pairing of MMX instructions (WinChip2)
 18-17	reserved
 16	enable return stack (default)
 15	disable bus pipelining #NA response
 14	disable data cache
 13	disable instruction cache
 12	enable branch predictions (WinChip2+)
 11	disable page directory cache
 10	reserved
 9	enable MMX instructions (default)
 8	enable data cache updates for PDE/PTE (C6)
 8	disable PDE/PTE update locking (WinChip2)
 7	disable check for self-modifying code
 6	enable linear burst mode
 5	disable #STPCLK support
 4	disable machine check exception
 3	disable power management
 2	enable #MC for internal errors
 1	set CPUID feature flag for CMPXCHG8 instruction
 0	reserved
SeeAlso: #R0039,#R0040
----------S00000108--------------------------
MSR 00000108h - Centaur (IDT) C6/WinChip2 - Feature Control Register #2
Size:	64 bits
SeeAlso: MSR 00000107h,MSR 00000109h

Bitfields for Centaur (IDT) C6/WinChip2 Feature Control Register #2:
Bit(s)	Description	(Table R0039)
 63-32	last four bytes of CPUID vendor ID string (see also #R0040)
 31-15	reserved
 14	use alternative CPUID vendor string
 13-12	reserved
 11-8	CPUID family
 7-4	CPUID model
 3-0	reserved
SeeAlso: #R0038,#R0039
----------S00000109--------------------------
MSR 00000109h - Centaur (IDT) C6/WinChip2 - Feature Control Register #3
Size:	30 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000108h,MSR 0000010Ah

Bitfields for Centaur (IDT) C6/WinChip2 Feature Control Register #3:
Bit(s)	Description	(Table R0040)
 63-32	first four bytes of CPUID vendor ID string
 31-0	middle four bytes of CPUID vendor ID string
SeeAlso: #R0039
----------S0000010A--------------------------
MSR 0000010Ah - IDT WinChip2 - Feature Control Register #4
Size:	6 bits
Access:	Read-Only
SeeAlso: MSR 00000109h

Bitfields for IDT WinChip2 Feature Control Register #4:
Bit(s)	Description	(Table R0066)
 63..6	Reserved
 5..2	DIVIDEND (if bus speed > 100MHz)
	DIVIDEND DIVISOR  multiplier_for_100Mhz_bus
	0101	    01		x2.33
	0011	    00		x2.5
	0110	    01		x2.66
	0100	    00		x3.0
	1000	    01		x3.33
	0101	    00		x3.5
	0110	    00		x4.0
	0111	    00		x4.5
 1..0	DIVISOR Fractional bus frequency multiplier
	00 = x2	       (on bus < 100 MHz multiplier based on
	01 = x3	       FCR4[1..0] only
	10 = x4
	11 = x5
----------S00000110--------------------------
MSR 00000110h - Centaur (IDT) C6/WinChip2 - Memory Configuration Register #0
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000111h,MSR 00000117h"Centaur"

Bitfields for Centaur (IDT) WinChip C6 Memory Configuration Register:
Bit(s)	Description	(Table R0041)
 63-44	base address of memory region
 43-32	reserved
 31-12	memory region mask
	(region is hit if (base AND address) == (mask AND address))
 11-5	reserved
 4-3	memory write order
	00 strong ordering
	01 weak for string
	10 weak for stack
	11 weak ordering for all writes
 2	enable write merging for stack writes
 1	enable write merging for string writes
 0	enable write merging for other writes
SeeAlso: #R0045
----------S00000111--------------------------
MSR 00000111h - Centaur (IDT) C6/WinChip2 - Memory Configuration Register #1
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000110h,MSR 00000112h,#R0041
----------S00000112--------------------------
MSR 00000112h - Centaur (IDT) C6/WinChip2 - Memory Configuration Register #2
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000111h,MSR 00000113h,#R0041
----------S00000113--------------------------
MSR 00000113h - Centaur (IDT) C6/WinChip2 - Memory Configuration Register #3
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000112h,MSR 00000114h,#R0041
----------S00000114--------------------------
MSR 00000114h - Centaur (IDT) C6/WinChip2 - Memory Configuration Register #4
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000113h,MSR 00000115h,#R0041
----------S00000115--------------------------
MSR 00000115h - Centaur (IDT) C6/WinChip2 - Memory Configuration Register #5
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000114h,MSR 00000116h"Centaur",#R0041
----------S00000116--------------------------
MSR 00000116h - PentiumII - "BBL_CR_ADDR" - SET L2 CACHE ADDRESS
Size:	32 bits
SeeAlso: MSR 00000088h,MSR 00000118h"PentiumII"

Bitfields for PentiumII "BBL_CR_ADDR":
Bit(s)	Description	(Table R0042)
 31-3	cache address bits 31-3 (docs say 35-3!)
 2-0	reserved (0) 
----------S00000116--------------------------
MSR 00000116h - Centaur (IDT) C6/WinChip2 - Memory Configuration Register #6