📄 gtdma.h
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/*******************************************************************************
* Copyright 2002, GALILEO TECHNOLOGY, LTD. *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
* *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI). *
********************************************************************************
* gtDma.h - DMA functions header and definitions
*
* DESCRIPTION:
* This file gives the user a complete interface to the powerful DMA engines,
* including functions for controling the priority mechanism.
* To fully understand the capabilities of the DMA engines please spare some
* time to go trough the spec.
*
* DEPENDENCIES:
* None.
*
*******************************************************************************/
#ifndef __INCgtDmah
#define __INCgtDmah
#ifndef __USING_GNU_CPP__
enum _bool {false,true};
#endif /* __USING_GNU_CPP__ */
/* includes */
#include "gt64260Def.h"
#define INCLUDE_DMA_4_7
#define NO_BIT 0x00000000
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define _16M 0x01000000
/* defines */
#define DMA_FIRST_ENGINE DMA_ENG_0
#ifdef INCLUDE_DMA_4_7
#define DMA_LAST_ENGINE DMA_ENG_7
#else
#define DMA_LAST_ENGINE DMA_ENG_3
#endif /* INCLUDE_DMA_4_7 */
#define IS_INVALID_ENGINE(engine) \
((engine) < DMA_FIRST_ENGINE || DMA_LAST_ENGINE < (engine))
/* typedefs */
typedef enum _dmaEngine{DMA_ENG_0, DMA_ENG_1, DMA_ENG_2, DMA_ENG_3
#ifdef INCLUDE_DMA_4_7
,DMA_ENG_4, DMA_ENG_5, DMA_ENG_6, DMA_ENG_7
#endif /* INCLUDE_DMA_4_7 */
} DMA_ENGINE;
/* status codes */
typedef enum _dmaStatus{DMA_CHANNEL_IDLE, DMA_CHANNEL_BUSY,
DMA_NO_SUCH_CHANNEL, DMA_OK, DMA_GENERAL_ERROR
} DMA_STATUS;
/*******************************************************************************
*
* Pizza arbiter slices Struct: Defined by user and used for updating the
* DMA Arbiter with priority for each channel.
* By default DMA_PIZZA is configured to ROUND_ROBIN.
* Each field represent one of 16 slices, in order to configurate it to one
* of the four engine simply write the engine number at the slice field.
*
*******************************************************************************/
typedef struct _dmaPizza0_3
{
unsigned char slice0;
unsigned char slice1;
unsigned char slice2;
unsigned char slice3;
unsigned char slice4;
unsigned char slice5;
unsigned char slice6;
unsigned char slice7;
unsigned char slice8;
unsigned char slice9;
unsigned char slice10;
unsigned char slice11;
unsigned char slice12;
unsigned char slice13;
unsigned char slice14;
unsigned char slice15;
} DMA_PIZZA0_3;
#ifdef INCLUDE_DMA_4_7
typedef struct _dmaPizza4_7
{
unsigned char slice0;
unsigned char slice1;
unsigned char slice2;
unsigned char slice3;
unsigned char slice4;
unsigned char slice5;
unsigned char slice6;
unsigned char slice7;
unsigned char slice8;
unsigned char slice9;
unsigned char slice10;
unsigned char slice11;
unsigned char slice12;
unsigned char slice13;
unsigned char slice14;
unsigned char slice15;
} DMA_PIZZA4_7;
#endif /* INCLUDE_DMA_4_7 */
/* dma descriptor structure */
typedef struct _dmaRecord
{
unsigned int ByteCnt;
unsigned int SrcAdd;
unsigned int DestAdd;
unsigned int NextRecPtr;
} DMA_RECORD;
/* Definitions for the low control register*/
/* DMA_DEST_DTL_8BYTES is defined as [0...2] == '001' (BIT1) while actually it
should be [0...2] == '000' (see the spec for more details). The main reason
for doing this is to be backwords competible. The function 'gtDmaTransfer'
will interpreter this configuration correctly and will set the destination
DTL to be 8 bytes. */
#define DMA_DEST_DTL_8BYTES BIT1
#define DMA_DEST_DTL_16BYTES BIT0
#define DMA_DEST_DTL_32BYTES (BIT0 | BIT1)
#define DMA_DEST_DTL_64BYTES (BIT0 | BIT1 | BIT2)
#define DMA_DEST_DTL_128BYTES BIT2
#define DMA_HOLD_SOURCE_ADDR BIT3
#define DMA_HOLD_DEST_ADDR BIT5
#define DMA_DTL_8BYTES NO_BIT
#define DMA_DTL_16BYTES BIT6
#define DMA_DTL_32BYTES (BIT6 | BIT7)
#define DMA_DTL_64BYTES (BIT6 | BIT7 | BIT8)
#define DMA_DTL_128BYTES BIT8
#define DMA_NON_CHAIN_MODE BIT9
#define DMA_CHAIN_MODE NO_BIT
#define DMA_INT_EVERY_NULL_POINTER BIT10
#define DMA_BLOCK_TRANSFER_MODE BIT11
#define DMA_DEMAND_MODE NO_BIT
#define DMA_CHANNEL_ENABLE BIT12
#define DMA_FETCH_NEXT_RECORD BIT13
#define DMA_ACTIVITY_STATUS BIT14
#define DMA_ALIGN_TOWARD_DEST BIT15
#define DMA_MASK_REQ BIT16
#define DMA_ENABLE_DESCRIPTOR BIT17
#define DMA_ENABLE_EOT BIT18
#define DMA_ENABLE_EOT_INTERRUPT BIT19
#define DMA_ABORT BIT20
#define DMA_SOURCE_ADDR_IN_PCI0 BIT21
#define DMA_DEST_ADDR_IN_PCI0 BIT23
#define DMA_REC_ADDR_IN_PCI0 BIT25
#define DMA_REQ_FROM_TIMER_COUNTER BIT28
#define DMA_REQ_FROM_MPP_PIN BIT28
#define DMA_OLD_DESCRIPTOR_MODE NO_BIT
#define DMA_NEW_DESCRIPTOR_MODE BIT31
#define DMA_ROUND_ROBIN 0xe4e4e4e4
#ifdef INCLUDE_PCI_1
#define DMA_SOURCE_ADDR_IN_PCI1 BIT22
#define DMA_DEST_ADDR_IN_PCI1 BIT24
#define DMA_REC_ADDR_IN_PCI1 BIT26
#endif /* INCLUDE_PCI_1 */
/* Performs DMA transfer according to: Engine, Byte Count,source & destination
Addresses and a pointer to the first descriptor (chain mode) */
DMA_STATUS gtDmaTransfer(DMA_ENGINE engine, unsigned int sourceAddr,
unsigned int destAddr, unsigned int numOfBytes,
unsigned int command, DMA_RECORD *pNextRecordPointer);
/* returns bit 14 in the dma control register. '1' - active '0' - not active */
DMA_STATUS gtDmaIsChannelActive(DMA_ENGINE engine);
/* Configured a command to a selected dma Engine. */
bool gtDmaCommand(DMA_ENGINE engine,unsigned int command);
/* Disable one of the DMA engines */
bool gtDmaEngineDisable(DMA_ENGINE engine);
/* The user fill the STRUCT DMA_PIZZA0_3 (see above), and this function update
it to the registers. */
bool gtDmaUpdateArbiter0_3(DMA_PIZZA0_3 *pDmaPizza);
#ifdef INCLUDE_DMA_4_7
bool gtDmaUpdateArbiter4_7(DMA_PIZZA4_7 *pDmaPizza);
#endif /* INCLUDE_DMA_4_7 */
#endif /* __INCgtDmah */
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