vxdmaintctrl.h

sbc7410的vxworksbsp

/*******************************************************************************
*                   Copyright 2002, GALILEO TECHNOLOGY, LTD.                   *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*                                                                              *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
********************************************************************************
* vxDmaIntCtrl.h - Header File for : DMA interrupt controller driver
*
* DESCRIPTION:
*       None.
*
* DEPENDENCIES:
*       None.
*
*******************************************************************************/

#ifndef __INCvxDmaIntCtrlh
#define __INCvxDmaIntCtrlh

/* includes */
#include <vxWorks.h>

/* defines  */
#ifndef STATUS
#define STATUS int
#endif

/* typedefs */


/* DMA_CAUSE is an enumerator that moves between 0 and 31/63. It summarize  */
/* both DMA cause registers into one virtual cause register sized 64. This  */
/* enumerator describes the cause bits positions in the DMA cause 			*/
/* registers.                                                               */             

typedef enum _dmaCause
{
    /* DMA channels 0-3 Interrupt cause register (0x8c0) */
    DMA_INT_CAUSE_START = -1		         , /* Cause low boundry */
    DMA_CHAN0_COMPLITION                     ,  
    DMA_CHAN0_ADDRESS_MISS                   ,  
    DMA_CHAN0_ACCESS_PROTECT_VIOLATION       ,
    DMA_CHAN0_WRITE_PROTECT                  ,
    DMA_CHAN0_DESCRIPTOR_OWNERSHIP_VIOLATION ,
    DMA_CHAN0_END_OF_TRANSFER                ,
    DMA_RESERVED0                            ,  
    DMA_RESERVED1                            ,  
    DMA_CHAN1_COMPLITION                     ,  
    DMA_CHAN1_ADDRESS_MISS                   ,  
    DMA_CHAN1_ACCESS_PROTECT_VIOLATION       ,
    DMA_CHAN1_WRITE_PROTECT                  ,
    DMA_CHAN1_DESCRIPTOR_OWNERSHIP_VIOLATION ,
    DMA_CHAN1_END_OF_TRANSFER                ,
    DMA_RESERVED2                            ,  
    DMA_RESERVED3                            ,  
    DMA_CHAN2_COMPLITION                     ,  
    DMA_CHAN2_ADDRESS_MISS                   ,  
    DMA_CHAN2_ACCESS_PROTECT_VIOLATION       ,
    DMA_CHAN2_WRITE_PROTECT                  ,
    DMA_CHAN2_DESCRIPTOR_OWNERSHIP_VIOLATION ,
    DMA_CHAN2_END_OF_TRANSFER                ,
    DMA_RESERVED4                            ,  
    DMA_RESERVED5                            ,  
    DMA_CHAN3_COMPLITION                     ,  
    DMA_CHAN3_ADDRESS_MISS                   ,  
    DMA_CHAN3_ACCESS_PROTECT_VIOLATION       ,
    DMA_CHAN3_WRITE_PROTECT                  ,
    DMA_CHAN3_DESCRIPTOR_OWNERSHIP_VIOLATION ,
    DMA_CHAN3_END_OF_TRANSFER                ,
    DMA_RESERVED6                            ,  
    DMA_RESERVED7                            ,  
    
#ifdef INCLUDE_DMA_4_7
    /* DMA channels 4-7 Interrupt cause register (0x9c0) */
    DMA_CHAN4_COMPLITION                     ,  
    DMA_CHAN4_ADDRESS_MISS                   ,  
    DMA_CHAN4_ACCESS_PROTECT_VIOLATION       ,
    DMA_CHAN4_WRITE_PROTECT                  ,
    DMA_CHAN4_DESCRIPTOR_OWNERSHIP_VIOLATION ,
    DMA_CHAN4_END_OF_TRANSFER                ,
    DMA_RESERVED8                            ,  
    DMA_RESERVED9                            ,  
    DMA_CHAN5_COMPLITION                     ,  
    DMA_CHAN5_ADDRESS_MISS                   ,  
    DMA_CHAN5_ACCESS_PROTECT_VIOLATION       ,
    DMA_CHAN5_WRITE_PROTECT                  ,
    DMA_CHAN5_DESCRIPTOR_OWNERSHIP_VIOLATION ,
    DMA_CHAN5_END_OF_TRANSFER                ,
    DMA_RESERVED10                           ,  
    DMA_RESERVED11                           ,  
    DMA_CHAN6_COMPLITION                     ,  
    DMA_CHAN6_ADDRESS_MISS                   ,  
    DMA_CHAN6_ACCESS_PROTECT_VIOLATION       ,
    DMA_CHAN6_WRITE_PROTECT                  ,
    DMA_CHAN6_DESCRIPTOR_OWNERSHIP_VIOLATION ,
    DMA_CHAN6_END_OF_TRANSFER                ,
    DMA_RESERVED12                           ,  
    DMA_RESERVED13                           ,  
    DMA_CHAN7_COMPLITION                     ,  
    DMA_CHAN7_ADDRESS_MISS                   ,  
    DMA_CHAN7_ACCESS_PROTECT_VIOLATION       ,
    DMA_CHAN7_WRITE_PROTECT                  ,
    DMA_CHAN7_DESCRIPTOR_OWNERSHIP_VIOLATION ,
    DMA_CHAN7_END_OF_TRANSFER                ,
    DMA_RESERVED14                           ,  
    DMA_RESERVED15                           ,  
#endif /* INCLUDE_DMA_4_7 */
    DMA_INT_CAUSE_END                          /* Cause high boundry */
} DMA_CAUSE;

        
/* vxDmaIntCtrl.h API list */
void    vxDmaIntCtrlInit (void); 
STATUS  vxDmaIntConnect  (DMA_CAUSE cause, VOIDFUNCPTR routine,
                          int parameter, int prio);
STATUS  vxDmaIntEnable   (DMA_CAUSE cause);
STATUS  vxDmaIntDisable  (DMA_CAUSE cause);

#endif /* __INCvxDmaIntCtrlh */