universe_dy4.h

sbc7410的vxworksbsp

/* VMEbus Slave Image 1 Bound Address Register */

#define VSI1_BD_MASK    0x0000ffff

/* VMEbus Slave Image 1 Translation Offset Register */

#define VSI1_TO_MASK    0x0000ffff

/* VMEbus Slave Image 2 Control */

#define VSI2_CTL_MASK           0x1f08ff3c      /* Reserved Bits */
#define VSI2_CTL_EN             (1 << 31)       /* Image Enable               */
#define VSI2_CTL_PWEN           (1 << 30)       /* Posted Write Enable        */
#define VSI2_CTL_PREN           (1 << 29)       /* Prefetch Read Enable       */
#define VSI2_CTL_AM_DATA        (1 << 22)       /* Respond to Data AM Code    */
#define VSI2_CTL_AM_PGM         (2 << 22)       /* Respond to Prog AM Code    */
#define VSI2_CTL_AM_SUPER       (2 << 20)       /* Respond to Superv AM Code  */
#define VSI2_CTL_AM_USER        (1 << 20)       /* Respond to Non-Priv AM Code*/
/*
#define VSI2_CTL_VAS_A16        (0 << 16)     */  /* Uninerse II does not support A16 
for VME slave Image 2, refer to UniverseII manuel for more details         */
#define VSI2_CTL_VAS_A24        (1 << 16)       /* Respond to VME A24         */
#define VSI2_CTL_VAS_A32        (2 << 16)       /* Respond to VME A32         */
#define VSI2_CTL_VAS_USER1      (6 << 16)       /* Respond to VME Space User 1*/
#define VSI2_CTL_VAS_USER2      (7 << 16)       /* Respond to VME Space User 2*/
#define VSI2_CTL_LD64EN         (1 << 7)        /* Enable 64-bit PCI bus Xfer */
#define VSI2_CTL_LLRMW          (1 << 6)        /* Enable PCI lock of VME RMW */
#define VSI2_CTL_LAS_MEM        (0 << 0)        /* PCIbus Memory Space        */
#define VSI2_CTL_LAS_IO         (1 << 0)        /* PCIbus I/O Space           */
#define VSI2_CTL_LAS_CFG        (2 << 0)        /* PCIbus Config Space        */

/* VMEbus Slave Image 2 Base Address Register */

#define VSI2_BS_MASK    0x0000ffff

/* VMEbus Slave Image 2 Bound Address Register */

#define VSI2_BD_MASK    0x0000ffff

/* VMEbus Slave Image 2 Translation Offset Register */

#define VSI2_TO_MASK    0x0000ffff

/* VMEbus Slave Image 3 Control */

#define VSI3_CTL_MASK           0x1f08ff3c      /* Reserved Bits */
#define VSI3_CTL_EN             (1 << 31)       /* Image Enable               */
#define VSI3_CTL_PWEN           (1 << 30)       /* Posted Write Enable        */
#define VSI3_CTL_PREN           (1 << 29)       /* Prefetch Read Enable       */
#define VSI3_CTL_AM_DATA        (1 << 22)       /* Respond to Data AM Code    */
#define VSI3_CTL_AM_PGM         (2 << 22)       /* Respond to Prog AM Code    */
#define VSI3_CTL_AM_SUPER       (2 << 20)       /* Respond to Superv AM Code  */
#define VSI3_CTL_AM_USER        (1 << 20)       /* Respond to Non-Priv AM Code*/
/*
#define VSI3_CTL_VAS_A16        (0 << 16)     */  /* Uninerse II does not support A16 
for VME slave Image 3, refer to UniverseII manuel for more details         */
#define VSI3_CTL_VAS_A24        (1 << 16)       /* Respond to VME A24         */
#define VSI3_CTL_VAS_A32        (2 << 16)       /* Respond to VME A32         */
#define VSI3_CTL_VAS_USER1      (6 << 16)       /* Respond to VME Space User 1*/
#define VSI3_CTL_VAS_USER2      (7 << 16)       /* Respond to VME Space User 2*/
#define VSI3_CTL_LD64EN         (1 << 7)        /* Enable 64-bit PCI bus Xfer */
#define VSI3_CTL_LLRMW          (1 << 6)        /* Enable PCI lock of VME RMW */
#define VSI3_CTL_LAS_MEM        (0 << 0)        /* PCIbus Memory Space        */
#define VSI3_CTL_LAS_IO         (1 << 0)        /* PCIbus I/O Space           */
#define VSI3_CTL_LAS_CFG        (2 << 0)        /* PCIbus Config Space        */

/* VMEbus Slave Image 3 Base Address Register */

#define VSI3_BS_MASK    0x0000ffff

/* VMEbus Slave Image 3 Bound Address Register */

#define VSI3_BD_MASK    0x0000ffff

/* VMEbus Slave Image 3 Translation Offset Register */

#define VSI3_TO_MASK    0x0000ffff



/* VMEbus Slave Image 4 Control */

#define VSI4_CTL_MASK           0xe0f700c3      /* Reserved Bits */
#define VSI4_CTL_EN             (1 << 31)       /* Image Enable               */
#define VSI4_CTL_PWEN           (1 << 30)       /* Posted Write Enable        */
#define VSI4_CTL_PREN           (1 << 29)       /* Prefetch Read Enable       */
#define VSI4_CTL_AM_DATA        (1 << 22)       /* Respond to Data AM Code    */
#define VSI4_CTL_AM_PGM         (2 << 22)       /* Respond to Prog AM Code    */
#define VSI4_CTL_AM_SUPER       (2 << 20)       /* Respond to Superv AM Code  */
#define VSI4_CTL_AM_USER        (1 << 20)       /* Respond to Non-Priv AM Code*/
#define VSI4_CTL_VAS_A16        (0 << 16)       /* Respond to VME A16         */
#define VSI4_CTL_VAS_A24        (1 << 16)       /* Respond to VME A24         */
#define VSI4_CTL_VAS_A32        (2 << 16)       /* Respond to VME A32         */
#define VSI4_CTL_VAS_USER1      (6 << 16)       /* Respond to VME Space User 1*/
#define VSI4_CTL_VAS_USER2      (7 << 16)       /* Respond to VME Space User 2*/
#define VSI4_CTL_LD64EN         (1 << 7)        /* Enable 64-bit PCI bus Xfer */
#define VSI4_CTL_LLRMW          (1 << 6)        /* Enable PCI lock of VME RMW */
#define VSI4_CTL_LAS_MEM        (0 << 0)        /* PCIbus Memory Space        */
#define VSI4_CTL_LAS_IO         (1 << 0)        /* PCIbus I/O Space           */
#define VSI4_CTL_LAS_CFG        (2 << 0)        /* PCIbus Config Space        */

/* VMEbus Slave Image 4 Base Address Register */

#define VSI4_BS_MASK        0xfffff000

/* VMEbus Slave Image 4 Bound Address Register */

#define VSI4_BD_MASK        0xfffff000

/* VMEbus Slave Image 4 Translation Offset Register */

#define VSI4_TO_MASK        0xfffff000


/* VMEbus Slave Image 5 Control */

#define VSI5_CTL_MASK           0xe0f700c3
#define VSI5_CTL_EN             (1 << 31)       /* Image Enable               */
#define VSI5_CTL_PWEN           (1 << 30)       /* Posted Write Enable        */
#define VSI5_CTL_PREN           (1 << 29)       /* Prefetch Read Enable       */
#define VSI5_CTL_AM_DATA        (1 << 22)       /* Respond to Data AM Code    */
#define VSI5_CTL_AM_PGM         (2 << 22)       /* Respond to Prog AM Code    */
#define VSI5_CTL_AM_SUPER       (2 << 20)       /* Respond to Superv AM Code  */
#define VSI5_CTL_AM_USER        (1 << 20)       /* Respond to Non-Priv AM Code*/
/*
#define VSI5_CTL_VAS_A16        (0 << 16)     */  /* Uninerse II does not support A16 
for VME slave Image 5, refer to UniverseII manuel for more details         */
#define VSI5_CTL_VAS_A24        (1 << 16)       /* Respond to VME A24         */
#define VSI5_CTL_VAS_A32        (2 << 16)       /* Respond to VME A32         */
#define VSI5_CTL_VAS_USER1      (6 << 16)       /* Respond to VME Space User 1*/
#define VSI5_CTL_VAS_USER2      (7 << 16)       /* Respond to VME Space User 2*/
#define VSI5_CTL_LD64EN         (1 << 7)        /* Enable 64-bit PCI bus Xfer */
#define VSI5_CTL_LLRMW          (1 << 6)        /* Enable PCI lock of VME RMW */
#define VSI5_CTL_LAS_MEM        (0 << 0)        /* PCIbus Memory Space        */
#define VSI5_CTL_LAS_IO         (1 << 0)        /* PCIbus I/O Space           */
#define VSI5_CTL_LAS_CFG        (2 << 0)        /* PCIbus Config Space        */

/* VMEbus Slave Image 5 Base Address Register */

#define VSI5_BS_MASK        0xffff0000

/* VMEbus Slave Image 5 Bound Address Register */

#define VSI5_BD_MASK        0xffff0000

/* VMEbus Slave Image 5 Translation Offset Register */

#define VSI5_TO_MASK        0xffff0000


/* VMEbus Slave Image 6 Control Mask */

#define VSI6_CTL_MASK           0xe0f700c3
#define VSI6_CTL_EN             (1 << 31)       /* Image Enable               */
#define VSI6_CTL_PWEN           (1 << 30)       /* Posted Write Enable        */
#define VSI6_CTL_PREN           (1 << 29)       /* Prefetch Read Enable       */
#define VSI6_CTL_AM_DATA        (1 << 22)       /* Respond to Data AM Code    */
#define VSI6_CTL_AM_PGM         (2 << 22)       /* Respond to Prog AM Code    */
#define VSI6_CTL_AM_SUPER       (2 << 20)       /* Respond to Superv AM Code  */
#define VSI6_CTL_AM_USER        (1 << 20)       /* Respond to Non-Priv AM Code*/
/*
#define VSI1_CTL_VAS_A16        (0 << 16)     */  /* Uninerse II does not support A16 
for VME slave Image 6, refer to UniverseII manuel for more details         */
#define VSI6_CTL_VAS_A24        (1 << 16)       /* Respond to VME A24         */
#define VSI6_CTL_VAS_A32        (2 << 16)       /* Respond to VME A32         */
#define VSI6_CTL_VAS_USER1      (6 << 16)       /* Respond to VME Space User 1*/
#define VSI6_CTL_VAS_USER2      (7 << 16)       /* Respond to VME Space User 2*/
#define VSI6_CTL_LD64EN         (1 << 7)        /* Enable 64-bit PCI bus Xfer */
#define VSI6_CTL_LLRMW          (1 << 6)        /* Enable PCI lock of VME RMW */
#define VSI6_CTL_LAS_MEM        (0 << 0)        /* PCIbus Memory Space        */
#define VSI6_CTL_LAS_IO         (1 << 0)        /* PCIbus I/O Space           */
#define VSI6_CTL_LAS_CFG        (2 << 0)        /* PCIbus Config Space        */

/* VMEbus Slave Image 6 Base Address Register */

#define VSI6_BS_MASK        0xffff0000

/* VMEbus Slave Image 6 Bound Address Register */

#define VSI6_BD_MASK        0xffff0000

/* VMEbus Slave Image 6 Translation Offset Register */

#define VSI6_TO_MASK        0xffff0000

/* VMEbus Slave Image 7 Control */

#define VSI7_CTL_MASK           0xe0f700c3
#define VSI7_CTL_EN             (1 << 31)       /* Image Enable               */
#define VSI7_CTL_PWEN           (1 << 30)       /* Posted Write Enable        */
#define VSI7_CTL_PREN           (1 << 29)       /* Prefetch Read Enable       */
#define VSI7_CTL_AM_DATA        (1 << 22)       /* Respond to Data AM Code    */
#define VSI7_CTL_AM_PGM         (2 << 22)       /* Respond to Prog AM Code    */
#define VSI7_CTL_AM_SUPER       (2 << 20)       /* Respond to Superv AM Code  */
#define VSI7_CTL_AM_USER        (1 << 20)       /* Respond to Non-Priv AM Code*/
/*
#define VSI7_CTL_VAS_A16        (0 << 16)     */  /* Uninerse II does not support A16 
for VME slave Image 7, refer to UniverseII manuel for more details         */
#define VSI7_CTL_VAS_A24        (1 << 16)       /* Respond to VME A24         */
#define VSI7_CTL_VAS_A32        (2 << 16)       /* Respond to VME A32         */
#define VSI7_CTL_VAS_USER1      (6 << 16)       /* Respond to VME Space User 1*/
#define VSI7_CTL_VAS_USER2      (7 << 16)       /* Respond to VME Space User 2*/
#define VSI7_CTL_LD64EN         (1 << 7)        /* Enable 64-bit PCI bus Xfer */
#define VSI7_CTL_LLRMW          (1 << 6)        /* Enable PCI lock of VME RMW */
#define VSI7_CTL_LAS_MEM        (0 << 0)        /* PCIbus Memory Space        */
#define VSI7_CTL_LAS_IO         (1 << 0)        /* PCIbus I/O Space           */
#define VSI7_CTL_LAS_CFG        (2 << 0)        /* PCIbus Config Space        */

/* VMEbus Slave Image 7 Base Address Register */

#define VSI7_BS_MASK        0xffff0000

/* VMEbus Slave Image 7 Bound Address Register */

#define VSI7_BD_MASK        0xffff0000

/* VMEbus Slave Image 7 Translation Offset Register */

#define VSI7_TO_MASK        0xffff0000

/* VMEbus Register Access Image Control Register */

#define VRAI_CTL_EN             (1 << 31)       /* Image Enable               */
#define VRAI_CTL_AM_DATA        (1 << 22)       /* Respond to Data AM Code    */
#define VRAI_CTL_AM_PGM         (2 << 22)       /* Respond to Prog AM Code    */
#define VRAI_CTL_AM_SUPER       (2 << 20)       /* Respond to Superv AM Code  */
#define VRAI_CTL_AM_USER        (1 << 20)       /* Respond to Non-Priv AM Code*/
#define VRAI_CTL_VAS_A16        (0 << 16)       /* Respond to VME A16         */
#define VRAI_CTL_VAS_A24        (1 << 16)       /* Respond to VME A24         */
#define VRAI_CTL_VAS_A32        (2 << 16)       /* Respond to VME A32         */
#define VRAI_CTL_VAS_USER1      (6 << 16)       /* Respond to VME Space User 1*/
#define VRAI_CTL_VAS_USER2      (7 << 16)       /* Respond to VME Space User 2*/

/* @prb */

/* VMEbus CSR Control Register */

#define VCSR_CTL_EN             (1 << 31)       /* Image Enable               */
#define VCSR_CTL_LAS_MEM        (0 << 0)        /* PCIbus Memory Space        */
#define VCSR_CTL_LAS_IO         (1 << 0)        /* PCIbus I/O Space           */
#define VCSR_CTL_LAS_CFG        (2 << 0)        /* PCIbus Config Space        */

/* VMEbus AM Code Error Log */

#define V_AMERR_MASK            0x07ffffff      /* Reserved bits */
#define V_AMERR_IACK            (1 << 25)       /*                            */
#define V_AMERR_M_ERR           (1 << 24)       /*                            */
#define V_AMERR_V_STAT          (1 << 23)       /*                            */

/* VMEbus CSR Bit Clear Register */

#define VCSR_CLR_MASK           0x1fffffff      /* Reserved bits */
#define VCSR_CLR_RESET          (1 << 31)       /* Negate PRST                */
#define VCSR_CLR_SYSFAIL        (1 << 30)       /* Negate SysFail             */
#define VCSR_CLR_FAIL           (1 << 29)       /* Board has Failed           */

/* VMEbus CSR Bit Set Register */

#define VCSR_SET_RESET          (1 << 31)       /* Assert PRST                */
#define VCSR_SET_SYSFAIL        (1 << 30)