universe_dy4.h

sbc7410的vxworksbsp

#define UNIVERSE_L_CMDERR       UNIVERSE_ADRS(0x18c)
#define UNIVERSE_LAERR          UNIVERSE_ADRS(0x190)
#define UNIVERSE_DCTL           UNIVERSE_ADRS(0x200)
#define UNIVERSE_DTBC           UNIVERSE_ADRS(0x204)
#define UNIVERSE_DLA            UNIVERSE_ADRS(0x208)
#define UNIVERSE_DVA            UNIVERSE_ADRS(0x210)
#define UNIVERSE_DCPP           UNIVERSE_ADRS(0x218)
#define UNIVERSE_DGCS           UNIVERSE_ADRS(0x220)
#define UNIVERSE_D_LLUE         UNIVERSE_ADRS(0x224)
#define UNIVERSE_LINT_EN        UNIVERSE_ADRS(0x300)
#define UNIVERSE_LINT_STAT      UNIVERSE_ADRS(0x304)
#define UNIVERSE_LINT_MAP0      UNIVERSE_ADRS(0x308)
#define UNIVERSE_LINT_MAP1      UNIVERSE_ADRS(0x30C)
#define UNIVERSE_VINT_EN        UNIVERSE_ADRS(0x310)
#define UNIVERSE_VINT_STAT      UNIVERSE_ADRS(0x314)
#define UNIVERSE_VINT_MAP0      UNIVERSE_ADRS(0x318)
#define UNIVERSE_VINT_MAP1      UNIVERSE_ADRS(0x31C)
#define UNIVERSE_STATID         UNIVERSE_ADRS(0x320)
#define UNIVERSE_V1_STATID      UNIVERSE_ADRS(0x324)
#define UNIVERSE_V2_STATID      UNIVERSE_ADRS(0x328)
#define UNIVERSE_V3_STATID      UNIVERSE_ADRS(0x32C)
#define UNIVERSE_V4_STATID      UNIVERSE_ADRS(0x330)
#define UNIVERSE_V5_STATID      UNIVERSE_ADRS(0x334)
#define UNIVERSE_V6_STATID      UNIVERSE_ADRS(0x338)
#define UNIVERSE_V7_STATID      UNIVERSE_ADRS(0x33C)
#define UNIVERSE_MAST_CTL       UNIVERSE_ADRS(0x400)
#define UNIVERSE_MISC_CTL       UNIVERSE_ADRS(0x404)
#define UNIVERSE_MISC_STAT      UNIVERSE_ADRS(0x408)
#define UNIVERSE_USER_AM        UNIVERSE_ADRS(0x40C)
#define UNIVERSE_VSI0_CTL       UNIVERSE_ADRS(0xF00)
#define UNIVERSE_VSI0_BS        UNIVERSE_ADRS(0xF04)
#define UNIVERSE_VSI0_BD        UNIVERSE_ADRS(0xF08)
#define UNIVERSE_VSI0_TO        UNIVERSE_ADRS(0xF0C)
#define UNIVERSE_VSI1_CTL       UNIVERSE_ADRS(0xF14)
#define UNIVERSE_VSI1_BS        UNIVERSE_ADRS(0xF18)
#define UNIVERSE_VSI1_BD        UNIVERSE_ADRS(0xF1C)
#define UNIVERSE_VSI1_TO        UNIVERSE_ADRS(0xF20)
#define UNIVERSE_VSI2_CTL       UNIVERSE_ADRS(0xF28)
#define UNIVERSE_VSI2_BS        UNIVERSE_ADRS(0xF2C)
#define UNIVERSE_VSI2_BD        UNIVERSE_ADRS(0xF30)
#define UNIVERSE_VSI2_TO        UNIVERSE_ADRS(0xF34)
#define UNIVERSE_VSI3_CTL       UNIVERSE_ADRS(0xF3C)
#define UNIVERSE_VSI3_BS        UNIVERSE_ADRS(0xF40)
#define UNIVERSE_VSI3_BD        UNIVERSE_ADRS(0xF44)
#define UNIVERSE_VSI3_TO        UNIVERSE_ADRS(0xF48)
#define UNIVERSE_VRAI_CTL       UNIVERSE_ADRS(0xF70)
#define UNIVERSE_VRAI_BS        UNIVERSE_ADRS(0xF74)
#define UNIVERSE_VCSR_CTL       UNIVERSE_ADRS(0xF80)
#define UNIVERSE_VCSR_TO        UNIVERSE_ADRS(0xF84)
#define UNIVERSE_V_AMERR        UNIVERSE_ADRS(0xF88)
#define UNIVERSE_VAERR          UNIVERSE_ADRS(0xF8C)
#define UNIVERSE_VCSR_CLR       UNIVERSE_ADRS(0xFF4)
#define UNIVERSE_VCSR_SET       UNIVERSE_ADRS(0xFF8)
#define UNIVERSE_VCSR_BS        UNIVERSE_ADRS(0xFFC)

/* NOW LET'S DEFINE THE BITS FOR THESE REGISTERS */

/* PCI MISC0 Register */

#define PCI_MISC0_LATENCY_TIMER 0x0000f800      /* max. value for timer */

/* PCI Configuration Space Control and Status Register */

#define PCI_CSR_MASK            0x007ffc00      /* Reserved bits */
#define PCI_CSR_D_PE            (1 << 31)       /* Detected/Clear Parity Error*/
#define PCI_CSR_S_SERR          (1 << 30)       /* Signalled SERR#            */
#define PCI_CSR_R_MA            (1 << 29)       /* Received Master Abort      */
#define PCI_CSR_R_TA            (1 << 28)       /* Received Target Abort      */
#define PCI_CSR_S_TA            (1 << 27)       /* Signalled Target Abort     */
#define PCI_CSR_DEVSEL_MEDIUM   (1 << 25)       /* Universe is medium speed   */
#define PCI_CSR_DP_D            (1 << 24)       /* Master detected/generated  */
                                                /* a data parity error        */
#define PCI_CSR_TFBBC           (1 << 23)       /* Target Fast Back to Back   */
                                                /* Capable (must be ?)        */
#define PCI_CSR_MFBBC           (1 << 9)        /* Master Fast Back to Back   */
                                                /* Capable (must be 0)        */
#define PCI_CSR_SERR_EN         (1 << 8)        /* Enable SERR# drivers       */
#define PCI_CSR_WAIT            (1 << 7)        /* Wait Cycle Control         */
#define PCI_CSR_PERSP           (1 << 6)        /* Enable Parity Error Resp   */
#define PCI_CSR_VGAPS           (1 << 5)        /* VGA Palette Snp (must be 0)*/
#define PCI_CSR_MWI_EN          (1 << 4)        /* Enable Memory Write and    */
                                                /* Invalidate (must be 0)     */
#define PCI_CSR_SC              (1 << 3)        /* Respond to Special Cycles  */
                                                /* (must be 0)                */
#define PCI_CSR_BM              (1 << 2)        /* Master Enable              */
#define PCI_CSR_MS              (1 << 1)        /* Target Memory Enable       */
#define PCI_CSR_IOS             (1)             /* Target I/O Enable          */

/* PCI Slave Image Control Register 0 */

#define LSI0_CTL_MASK           0x3f380efc      /* Mask bits */
#define LSI0_CTL_EN             (1 << 31)       /* Enable PCI Slave Image     */
#define LSI0_CTL_WP             (1 << 30)       /* Enable Posted Writes       */
#define LSI0_CTL_D8             (0 << 22)       /* Max VME Data Width = 8     */
#define LSI0_CTL_D16            (1 << 22)       /* Max VME Data Width = 16    */
#define LSI0_CTL_D32            (2 << 22)       /* Max VME Data Width = 32    */
#define LSI0_CTL_D64            (3 << 22)       /* Max VME Data Width = 64    */
#define LSI0_CTL_A16            (0 << 16)       /* VME Address Space A16      */
#define LSI0_CTL_A24            (1 << 16)       /* VME Address Space A24      */
#define LSI0_CTL_A32            (2 << 16)       /* VME Address Space A32      */
#define LSI0_CTL_CSR            (5 << 16)       /* VME Address Space CSR      */
#define LSI0_CTL_USER1          (6 << 16)       /* VME Address Space USER 1   */
#define LSI0_CTL_USER2          (7 << 16)       /* VME Address Space USER 2   */
#define LSI0_CTL_PGM            (1 << 14)       /* Program AM Code            */
#define LSI0_CTL_DATA           (0 << 14)       /* Data AM Code               */
#define LSI0_CTL_SUP            (1 << 12)       /* Supervisor AM Code         */
#define LSI0_CTL_USR            (0 << 12)       /* User AM Code               */
#define LSI0_CTL_BLK            (1 << 8)        /* Supervisor AM Code         */
#define LSI0_CTL_SINGLE         (0 << 8)        /* User AM Code               */
#define LSI0_CTL_PCI_MEM        (0 << 0)        /* PCI Memory Space           */
#define LSI0_CTL_PCI_IO         (1 << 0)        /* PCI I/O Space              */
#define LSI0_CTL_PCI_CONFIG     (2 << 0)        /* PCI Type 1 Config Space    */

/* PCI Slave Image Base Address Register 0 */

#define LSI0_BS_MASK    0x00000fff

/* PCI Slave Image Bound Address Register 0 */

#define LSI0_BD_MASK    0x00000fff

/* PCI Slave Image Translation Offset Register 0 */

#define LSI0_TO_MASK    0x00000fff

/* PCI Slave Image Control Register 1 */

#define LSI1_CTL_MASK           0x3f380efc      /* Mask bits */
#define LSI1_CTL_EN             (1 << 31)       /* Enable PCI Slave Image     */
#define LSI1_CTL_WP             (1 << 30)       /* Enable Posted Writes       */
#define LSI1_CTL_D8             (0 << 22)       /* Max VME Data Width = 8     */
#define LSI1_CTL_D16            (1 << 22)       /* Max VME Data Width = 16    */
#define LSI1_CTL_D32            (2 << 22)       /* Max VME Data Width = 32    */
#define LSI1_CTL_D64            (3 << 22)       /* Max VME Data Width = 64    */
#define LSI1_CTL_A16            (0 << 16)       /* VME Address Space A16      */
#define LSI1_CTL_A24            (1 << 16)       /* VME Address Space A24      */
#define LSI1_CTL_A32            (2 << 16)       /* VME Address Space A32      */
#define LSI1_CTL_CSR            (5 << 16)       /* VME Address Space CSR      */
#define LSI1_CTL_USER1          (6 << 16)       /* VME Address Space USER 1   */
#define LSI1_CTL_USER2          (7 << 16)       /* VME Address Space USER 2   */
#define LSI1_CTL_PGM            (1 << 14)       /* Program AM Code            */
#define LSI1_CTL_DATA           (0 << 14)       /* Data AM Code               */
#define LSI1_CTL_SUP            (1 << 12)       /* Supervisor AM Code         */
#define LSI1_CTL_USR            (0 << 12)       /* User AM Code               */
#define LSI1_CTL_BLK            (1 << 8)        /* Supervisor AM Code         */
#define LSI1_CTL_SINGLE         (0 << 8)        /* User AM Code               */
#define LSI1_CTL_PCI_MEM        (0 << 0)        /* PCI Memory Space           */
#define LSI1_CTL_PCI_IO         (1 << 0)        /* PCI I/O Space              */
#define LSI1_CTL_PCI_CONFIG     (2 << 0)        /* PCI Type 1 Config Space    */

/* PCI Slave Image Base Address Register 1 */

#define LSI1_BS_MASK    0x0000ffff

/* PCI Slave Image Bound Address Register 1 */

#define LSI1_BD_MASK    0x0000ffff

/* PCI Slave Image Translation Offset Register 1 */

#define LSI1_TO_MASK    0x0000ffff

/* PCI Slave Image Control Register 2 */

#define LSI2_CTL_MASK           0x3f380efc      /* Mask bits */
#define LSI2_CTL_EN             (1 << 31)       /* Enable PCI Slave Image     */
#define LSI2_CTL_WP             (1 << 30)       /* Enable Posted Writes       */
#define LSI2_CTL_D8             (0 << 22)       /* Max VME Data Width = 8     */
#define LSI2_CTL_D16            (1 << 22)       /* Max VME Data Width = 16    */
#define LSI2_CTL_D32            (2 << 22)       /* Max VME Data Width = 32    */
#define LSI2_CTL_D64            (3 << 22)       /* Max VME Data Width = 64    */
#define LSI2_CTL_A16            (0 << 16)       /* VME Address Space A16      */
#define LSI2_CTL_A24            (1 << 16)       /* VME Address Space A24      */
#define LSI2_CTL_A32            (2 << 16)       /* VME Address Space A32      */
#define LSI2_CTL_CSR            (5 << 16)       /* VME Address Space CSR      */
#define LSI2_CTL_USER1          (6 << 16)       /* VME Address Space USER 1   */
#define LSI2_CTL_USER2          (7 << 16)       /* VME Address Space USER 2   */
#define LSI2_CTL_PGM            (1 << 14)       /* Program AM Code            */
#define LSI2_CTL_DATA           (0 << 14)       /* Data AM Code               */
#define LSI2_CTL_SUP            (1 << 12)       /* Supervisor AM Code         */
#define LSI2_CTL_USR            (0 << 12)       /* User AM Code               */
#define LSI2_CTL_BLK            (1 << 8)        /* Supervisor AM Code         */
#define LSI2_CTL_SINGLE         (0 << 8)        /* User AM Code               */
#define LSI2_CTL_PCI_MEM        (0 << 0)        /* PCI Memory Space           */
#define LSI2_CTL_PCI_IO         (1 << 0)        /* PCI I/O Space              */
#define LSI2_CTL_PCI_CONFIG     (2 << 0)        /* PCI Type 1 Config Space    */

/* PCI Slave Image Base Address Register 2 */

#define LSI2_BS_MASK    0x0000ffff

/* PCI Slave Image Bound Address Register 2 */

#define LSI2_BD_MASK    0x0000ffff

/* PCI Slave Image Translation Offset Register 2 */

#define LSI2_TO_MASK    0x0000ffff

/* PCI Slave Image Control Register 3 */

#define LSI3_CTL_MASK           0x3f380efc      /* Mask bits */
#define LSI3_CTL_EN             (1 << 31)       /* Enable PCI Slave Image     */
#define LSI3_CTL_WP             (1 << 30)       /* Enable Posted Writes       */
#define LSI3_CTL_D8             (0 << 22)       /* Max VME Data Width = 8     */
#define LSI3_CTL_D16            (1 << 22)       /* Max VME Data Width = 16    */
#define LSI3_CTL_D32            (2 << 22)       /* Max VME Data Width = 32    */
#define LSI3_CTL_D64            (3 << 22)       /* Max VME Data Width = 64    */
#define LSI3_CTL_A16            (0 << 16)       /* VME Address Space A16      */
#define LSI3_CTL_A24            (1 << 16)       /* VME Address Space A24      */
#define LSI3_CTL_A32            (2 << 16)       /* VME Address Space A32      */
#define LSI3_CTL_CSR            (5 << 16)       /* VME Address Space CSR      */
#define LSI3_CTL_USER1          (6 << 16)       /* VME Address Space USER 1   */
#define LSI3_CTL_USER2          (7 << 16)       /* VME Address Space USER 2   */
#define LSI3_CTL_PGM            (1 << 14)       /* Program AM Code            */
#define LSI3_CTL_DATA           (0 << 14)       /* Data AM Code               */
#define LSI3_CTL_SUP            (1 << 12)       /* Supervisor AM Code         */
#define LSI3_CTL_USR            (0 << 12)       /* User AM Code               */
#define LSI3_CTL_BLK            (1 << 8)        /* Supervisor AM Code         */
#define LSI3_CTL_SINGLE         (0 << 8)        /* User AM Code               */
#define LSI3_CTL_PCI_MEM        (0 << 0)        /* PCI Memory Space           */
#define LSI3_CTL_PCI_IO         (1 << 0)        /* PCI I/O Space              */
#define LSI3_CTL_PCI_CONFIG     (2 << 0)        /* PCI Type 1 Config Space    */

/* PCI Slave Image Base Address Register 3 */

#define LSI3_BS_MASK    0x0000ffff

/* PCI Slave Image Bound Address Register 3 */

#define LSI3_BD_MASK    0x0000ffff

/* PCI Slave Image Translation Offset Register 3 */

#define LSI3_TO_MASK    0x0000ffff


/* PCI Slave Image Control Register 4 */

#define LSI4_CTL_MASK           0x3f380efc      /* Mask bits */
#define LSI4_CTL_EN             (1 << 31)       /* Enable PCI Slave Image     */
#define LSI4_CTL_WP             (1 << 30)       /* Enable Posted Writes       */
#define LSI4_CTL_D8             (0 << 22)       /* Max VME Data Width = 8     */
#define LSI4_CTL_D16            (1 << 22)       /* Max VME Data Width = 16    */
#define LSI4_CTL_D32            (2 << 22)       /* Max VME Data Width = 32    */
#define LSI4_CTL_D64            (3 << 22)       /* Max VME Data Width = 64    */
#define LSI4_CTL_A16            (0 << 16)       /* VME Address Space A16      */
#define LSI4_CTL_A24            (1 << 16)       /* VME Address Space A24      */
#define LSI4_CTL_A32            (2 << 16)       /* VME Address Space A32      */
#define LSI4_CTL_CSR            (5 << 16)       /* VME Address Space CSR      */
#define LSI4_CTL_USER1          (6 << 16)       /* VME Address Space USER 1   */
#define LSI4_CTL_USER2          (7 << 16)       /* VME Address Space USER 2   */
#define LSI4_CTL_PGM            (1 << 14)       /* Program AM Code            */
#define LSI4_CTL_DATA           (0 << 14)       /* Data AM Code               */
#define LSI4_CTL_SUP            (1 << 12)       /* Supervisor AM Code         */
#define LSI4_CTL_USR            (0 << 12)       /* User AM Code               */
#define LSI4_CTL_BLK            (1 << 8)        /* Supervisor AM Code         */
#define LSI4_CTL_SINGLE         (0 << 8)        /* User AM Code               */
#define LSI4_CTL_PCI_MEM        (0 << 0)        /* PCI Memory Space           */
#define LSI4_CTL_PCI_IO         (1 << 0)        /* PCI I/O Space              */
#define LSI4_CTL_PCI_CONFIG     (2 << 0)        /* PCI Type 1 Config Space    */

/* PCI Slave Image Base Address Register 3 */