universe_dy4.h

sbc7410的vxworksbsp

/* universe_dy4.h - VMEbus Interface Controller */

/* Copyright, 1996-1997 Wind River Systems, Inc. */
/* Copyright 2001 DY 4 Systems, Inc. */

/*
modification history
--------------------
01c,23sep02,tis  -added special slave image regions masks
                 -added masks for VSI4,VSI5,VSI6,VSI7,LSI4,LSI5,LSI6,and LSI7 PT#1272
01b,20sep01,tis  added priority Interrupt level mask and LINT_STAT_RESET,
                 VINT_STAT_RESET (PT#798, PT#800)
01a,05jul97,dy4  written from (mv2604/universe.h ver 01c).
*/

#ifndef INCuniverseh
#define INCuniverseh

/*
This file contains constants for the Universe PCI-VME interface chip.
The macro UNIVERSE_BASE_ADRS must be defined when including this header.

The registers are listed in ascending (numerical) order; the definitions
for each register are started with a header eg.
*/
#ifdef __cplusplus
extern "C" {
#endif


#ifdef  _ASMLANGUAGE
#define CASTINT
#else
#define CASTINT (UINT *)
#endif  /* _ASMLANGUAGE */

/*
 * on-board access, register definitions
 * these registers MUST BE WRITTEN 4-BYTE WRITES ONLY
 * they can be read as byte, two-bytes or 4-bytes.
 */

#ifndef UNIVERSE_ADRS   /* to permit alternative board addressing */
#define UNIVERSE_ADRS(reg)   (CASTINT (UNIVERSE_BASE_ADRS + reg )) 
#endif  /* UNIVERSE_ADRS */

#ifndef UNIV_BUS_ADRS   /* to permit alternative board addressing */
#define UNIV_BUS_ADRS(reg)      (CASTINT (UNIV_BUS_BASE_ADRS + (reg)))
#endif  /* UNIV_BUS_ADRS */

#ifndef _ASMLANGUAGE

typedef struct
    {
    UINT32 *regAddr;                   /* Address of register */
    UINT32 regVal;                     /* Value of register */
    UINT32 regMask;                    /* Mask value of register */
    } UNIVERSE_REG_TYPE;

typedef struct
    {
    UINT32     pciBs;                  /* PCI_BS */
    UINT32     mastCtl;                /* MAST_CTL */
    UINT32     miscCtl;                /* MISC_CTL */
    UNIVERSE_REG_TYPE  pciLsi[4][4];   /* LSIx Registers */
    } UNIVERSE_CNFG_HDR;

#endif /*_ASMLANGUAGE*/

/* VME interrupt level definitions */

#define	LVL0			0x0001
#define LVL1			0x0002
#define LVL2			0x0004
#define LVL3			0x0008
#define LVL4			0x0010
#define LVL5			0x0020
#define LVL6			0x0040
#define LVL7			0x0080

/* additional VME interrupts supported by the UNIVERSE chip */

#define UNIVERSE_DMA_INT		0x0100  /* bit setting for DMA intr */
#define UNIVERSE_LERR_INT		0x0200  /* bit setting for PCI bus err intr */
#define UNIVERSE_VERR_INT		0x0400  /* bit setting for VMEbus err int */
#define UNIVERSE_VME_SW_IACK_INT 0x1000  /* bit setting for VME SW IACK intr */
#define UNIVERSE_PCI_SW_INT		0x2000  /* bit setting for SW intr */
#define UNIVERSE_SYSFAIL_INT	0x4000  /* bit setting for SYSFAIL intr */
#define UNIVERSE_ACFAIL_INT		0x8000  /* bit setting for ACFAIL intr */

#define UNIVERSE_INT_MASK		0x0000f700  /* mask for the interrupts */
											/* defined above */

#define UNIVERSE_CNFG_OFFSET    0x100   /* offset VME specific part */

/* WRITES MUST BE 4-BYTE WRITES ONLY */

/*
 * Device ID - Newbridge allocated device ident    0x00    31-16
 * Vendor ID - PCI SIG allocated vendor identifier 0x00    15-00
 */

#define UNIVERSE_PCI_ID         UNIVERSE_ADRS(0x00)

/* PCI Configuration Space Control and Status Reg  0x00    31-00 */

#define UNIVERSE_PCI_CSR        UNIVERSE_ADRS(0x04)

/*
 * PCI Configuration Class Register
 * PCI Base Class Code - "PCI bridge device"       0x10    31-24
 * PCI Sub Class Code - "other bridge device"      0x10    23-16
 * PCI Programming Interface - (Not Applicable)    0x10    15-08
 * Revision ID                                     0x10    07-00
 */

#define UNIVERSE_PCI_CLASS      UNIVERSE_ADRS(0x08)

/* PCI Configuration Miscellaneous 0 Register      0x00    31-00 */

#define UNIVERSE_PCI_MISC0      UNIVERSE_ADRS(0x0c)

/*
 * PCI Base Address Register                       0x08    31-16
 * PCI Bus Address Space Register                  0x08    15-00
 */

#define UNIVERSE_PCI_BS         UNIVERSE_ADRS(0x10)

/* PCI Configuration Miscellaneous 1 Register      0x00    31-00 */

#define UNIVERSE_PCI_MISC1      UNIVERSE_ADRS(0x3c)

/* PCI Slave Image 0 Control Register              0x100   31-00 */

#define UNIVERSE_LSI0_CTL       UNIVERSE_ADRS(0x100)

/*
 * PCI Slave Image 0 Base Address Register         0x104   31-12
 * Universe Reserved                               0x104   11-00
 */

#define UNIVERSE_LSI0_BS        UNIVERSE_ADRS(0x104)

/*
 * PCI Slave Image 0 Bound Address Register        0x108   31-12
 * Universe Reserved                               0x108   11-00
 */

#define UNIVERSE_LSI0_BD        UNIVERSE_ADRS(0x108)

/*
 * PCI Slave Image 0 Translation Offset            0x10C   31-12
 * Universe Reserved                               0x10C   11-00
 */

#define UNIVERSE_LSI0_TO        UNIVERSE_ADRS(0x10c)

/* PCI Slave Image 1 Control Register              0x114   31-00 */

#define UNIVERSE_LSI1_CTL       UNIVERSE_ADRS(0x114)

/*
 * PCI Slave Image 1 Base Address Register         0x118   31-12
 * Universe Reserved                               0x118   11-00
 */

#define UNIVERSE_LSI1_BS        UNIVERSE_ADRS(0x118)

/*
 * PCI Slave Image 1 Bound Address Register        0x11C   31-12
 * Universe Reserved                               0x11C   11-00
 */

#define UNIVERSE_LSI1_BD        UNIVERSE_ADRS(0x11C)

/*
 * PCI Slave Image 1 Translation Offset            0x120   31-12
 * Universe Reserved                               0x120   11-00
 */

#define UNIVERSE_LSI1_TO        UNIVERSE_ADRS(0x120)

/* PCI Slave Image 2 Control Register              0x128   31-00 */

#define UNIVERSE_LSI2_CTL       UNIVERSE_ADRS(0x128)

/*
 * PCI Slave Image 2 Base Address Register         0x12C   31-12
 * Universe Reserved                               0x12C   11-00
 */

#define UNIVERSE_LSI2_BS        UNIVERSE_ADRS(0x12C)

/*
 * PCI Slave Image 2 Bound Address Register        0x130   31-12
 * Universe Reserved                               0x130   11-00
 */

#define UNIVERSE_LSI2_BD        UNIVERSE_ADRS(0x130)

/*
 * PCI Slave Image 2 Translation Offset            0x134   31-12
 * Universe Reserved                               0x134   11-00
 */

#define UNIVERSE_LSI2_TO        UNIVERSE_ADRS(0x134)

/* PCI Slave Image 3 Control Register              0x13C   31-00 */

#define UNIVERSE_LSI3_CTL       UNIVERSE_ADRS(0x13C)

/*
 * PCI Slave Image 3 Base Address Register         0x140   31-12
 * Universe Reserved                               0x140   11-00
 */

#define UNIVERSE_LSI3_BS        UNIVERSE_ADRS(0x140)

/*
 * PCI Slave Image 3 Bound Address Register        0x144   31-12
 * Universe Reserved                               0x144   11-00
 */

#define UNIVERSE_LSI3_BD        UNIVERSE_ADRS(0x144)

/*
 * PCI Slave Image 3 Translation Offset            0x148   31-12
 * Universe Reserved                               0x148   11-00
 */

#define UNIVERSE_LSI3_TO        UNIVERSE_ADRS(0x148)

/*
 * Universe Reserved                               0x170   31-02
 * Special Cycle                                   0x170   01-00
 */

#define UNIVERSE_SCYC_CTL       UNIVERSE_ADRS(0x170)

/*
 * Address for Special Cycle                       0x174   31-02
 * Universe Reserved                               0x174   01-00
 */

#define UNIVERSE_SCYC_ADDR      UNIVERSE_ADRS(0x174)

/* Special Cycle Bit Enable Mask                   0x178   31-00 */

#define UNIVERSE_SCYC_EN        UNIVERSE_ADRS(0x178)

/* Special Cycle Compare Register                  0x178   31-00 */

#define UNIVERSE_SCYC_CMP       UNIVERSE_ADRS(0x17c)

/* Special Cycle Swap Register                     0x178   31-00 */

#define UNIVERSE_SCYC_SWP       UNIVERSE_ADRS(0x180)

/* Other Registers */

#define UNIVERSE_LMISC          UNIVERSE_ADRS(0x184)
#define UNIVERSE_SLSI           UNIVERSE_ADRS(0x188)