vxdmaintctrl.c

sbc7410的vxworksbsp

        if(i == 0 || intCauseArray[i-1].prio < prio) /* Make connection */
        {
            intCauseArray[i].causeBit = SWAP_CAUSE_BIT(cause);
            intCauseArray[i].userISR  = routine;
            intCauseArray[i].arg      = parameter;
            intCauseArray[i].prio     = prio;
            (*intConnectCount)++;
            break;
        }
        else
        {
            /* Push the low priority connection down the table */
            intCauseArray[i].causeBit = intCauseArray[i-1].causeBit;
            intCauseArray[i].userISR  = intCauseArray[i-1].userISR;
            intCauseArray[i].arg      = intCauseArray[i-1].arg;
            intCauseArray[i].prio     = intCauseArray[i-1].prio;    
        }
    }

    intUnlock(sysIntOldConfig);
    return OK;
}

/*******************************************************************************
* vxDmaIntEnable - Enable a DMA interrupt
*
* DESCRIPTION:
*       This routine unmasks a specified DMA interrupt cause on the appropriate  
*       mask register.
*       The routine will preform argument validity check. 
*
* INPUT:
*       cause - DMA interrupt cause as defined in DMA_CAUSE.  
*
* OUTPUT:
*       The appropriate bit in the appropriate mask register is set.
*
* RETURN:
*       OK    - If the bit was unmasked
*       ERROR - if the bit was invalid
*
*******************************************************************************/
STATUS vxDmaIntEnable(DMA_CAUSE cause)
{
    volatile UINT32 *maskReg;         /* The issued mask register */           

    if(DMA0_3_CAUSE)
        maskReg = &DMA0_3_MASK_REG;   
#ifdef INCLUDE_DMA_4_7
    else if(DMA4_7_CAUSE)
        maskReg = &DMA4_7_MASK_REG;
#endif
    else
    {
        logMsg("\nvxDmaIntEnable: Invalid cause %d\n", cause,0,0,0,0,0);
        return ERROR;
    }
        
    *maskReg |= SWAP_CAUSE_BIT(cause);
    return OK;
}

/*******************************************************************************
* vxDmaIntDisable - Disable a DMA interrupt
*
* DESCRIPTION:
*       This routine masks a specified DMA interrupt cause on the appropriate 
*       mask register.
*       The routine will preform argument validity check. 
*
* INPUT:
*       cause - DMA interrupt cause as defined in DMA_CAUSE. 
*
* OUTPUT:
*       The appropriate bit in the appropriate mask register is reset.
*
* RETURN:
*       OK    - If the bit was masked
*       ERROR - if the bit was invalid
*
*******************************************************************************/
STATUS vxDmaIntDisable(DMA_CAUSE cause)
{
    volatile UINT32 *maskReg;       /* The issued mask register */

    if(DMA0_3_CAUSE)
        maskReg = &DMA0_3_MASK_REG; 
#ifdef INCLUDE_DMA_4_7
    else if(DMA4_7_CAUSE)
        maskReg = &DMA4_7_MASK_REG;  
#endif
    else
    {
        logMsg("\nvxDmaIntDisable: Invalid cause %d\n", cause,0,0,0,0,0);
        return ERROR;
    }
        
    *maskReg &= ~(SWAP_CAUSE_BIT(cause));
    return OK;
}

/*******************************************************************************
* dma0_1CompInt - DMA 0-1 completion interrupt controller routine.
*
* DESCRIPTION:
*       This routine handles the DMA 0-1 completion interrupts. 
*       As soon as the interrupt signal is active the CPU analyzes the GT DMA 
*       0-3 Interrupt Cause register in order to locate the originating 
*       interrupt event. 
*       Then the routine calls the user specified service routine for that 
*       interrupt cause.
*       The function scans the dma0_1Array[] (dma0_1Count valid entries)
*       trying to find a hit in the dma0_1Array cause table.
*       When found, the ISR in the same entry is executed.
*
* INPUT:
*       None.
*
* OUTPUT:
*       If a cause bit is active and it's connected to an ISR function,
*       the function will be called.
*
* RETURN:
*       None.
*
*******************************************************************************/
void dma0_1CompInt (void)
{
    int     i; 
    unsigned int causeAndMask;

    /* Cause bit is active if an interrupt occured and the bit is unmasked. */
    causeAndMask = DMA0_3_CAUSE_REG & DMA0_3_MASK_REG ;

    for(i = 0; i < dma0_1Count; i++)

        if(causeAndMask & dma0_1Array[i].causeBit)
        {
            /* Perform the ISR */
            (*dma0_1Array[i].userISR) (dma0_1Array[i].arg);

            /* Reset the interrutp cause bit in the DMA cause register */
            DMA0_3_CAUSE_REG = ~(dma0_1Array[i].causeBit);
        }                                                            
}

/*******************************************************************************
* dma2_3CompInt - DMA 2-3 completion Interrupt controller routine.
*
* DESCRIPTION:
*       This routine handles the DMA 2-3 completion interrupts. 
*       As soon as the interrupt signal is active the CPU analyzes the GT DMA 
*       0-3 Interrupt Cause register in order to locate the originating
*       interrupt  event. 
*       Then the routine calls the user specified service routine for that 
*       interrupt cause.
*       The function scans the dma2_3Array[] (dma2_3Count valid entries)
*       trying to find a hit in the dma0_1Array cause table.
*       When found, the ISR in the same entry is executed.
*       
* INPUT:
*       None.
*
* OUTPUT:
*       If a cause bit is active and it's connected to an ISR function,
*       the function will be called.
*
* RETURN:
*       None.
*
*******************************************************************************/
void dma2_3CompInt (void)
{
    int     i;          
    unsigned int causeAndMask;

    /* Cause bit is active if an interrupt occured and the bit is unmasked. */
    causeAndMask = DMA0_3_CAUSE_REG & DMA0_3_MASK_REG ;

    for(i = 0; i < dma2_3Count; i++)

        if(causeAndMask & dma2_3Array[i].causeBit)
        {
            /* Perform the ISR */
            (*dma2_3Array[i].userISR) (dma2_3Array[i].arg);

            /* Reset the interrutp cause bit in the DMA cause register */
            DMA0_3_CAUSE_REG = ~(dma2_3Array[i].causeBit);
        }
}

#ifdef INCLUDE_DMA_4_7
/*******************************************************************************
* dma4_5CompInt - DMA 4-5 completion Interrupt controller routine.
*
* DESCRIPTION:
*       This routine handles the DMA 4-5 completion interrupts. 
*       As soon as the interrupt signal is active the CPU analyzes the GT DMA 
*       4-7 Interrupt Cause register in order to locate the originating  
*       interrupt event. 
*       Then the routine calls the user specified service routine for that 
*       interrupt cause.
*       The function scans the dma4_5Array[] (dma4_5Count valid entries)
*       trying to find a hit in the dma4_5Array cause table.
*       When found, the ISR in the same entry is executed.
*
* INPUT:
*       None.
*
* OUTPUT:
*       If a cause bit is active and it's connected to an ISR function,
*       the function will be called.
*
* RETURN:
*       None.
*
*******************************************************************************/
void dma4_5CompInt (void)
{
    int     i;          
    unsigned int causeAndMask;

    /* Cause bit is active if an interrupt occured and the bit is unmasked. */
    causeAndMask = DMA4_7_CAUSE_REG & DMA4_7_MASK_REG ;

    for(i = 0; i < dma4_5Count; i++)
        
        if(causeAndMask & dma4_5Array[i].causeBit)
        {
            /* Perform the ISR */
            (*dma4_5Array[i].userISR) (dma4_5Array[i].arg);

            /* Reset the interrutp cause bit in the DMA cause register */
            DMA4_7_CAUSE_REG = ~(dma4_5Array[i].causeBit);
        }
}

/*******************************************************************************
* dma6_7CompInt - DMA 6-7 completion interrupt controller routine.
*
* DESCRIPTION:
*       This routine handles the DMA 6-7 completion interrupts. 
*       As soon as the interrupt signal is active the CPU analyzes the GT DMA 
*       4-7 Interrupt Cause register in order to locate the originating  
*       interrupt event. 
*       Then the routine calls the user specified service routine for that 
*       interrupt cause.
*       The function scans the dma6_7Array[] (dma6_7Count valid entries)
*       trying to find a hit in the dma6_7Array cause table.
*       When found, the ISR in the same entry is executed.
*
* INPUT:
*       None.
*
* OUTPUT:
*       If a cause bit is active and it's connected to an ISR function,
*       the function will be called.
*
* RETURN:
*       None.
*
*******************************************************************************/
void dma6_7CompInt (void)
{
    int     i;          
    unsigned int causeAndMask;

    /* Cause bit is active if an interrupt occured and the bit is unmasked. */
    causeAndMask = DMA4_7_CAUSE_REG & DMA4_7_MASK_REG;

    for(i = 0; i < dma6_7Count; i++)
        
        if(causeAndMask & dma6_7Array[i].causeBit)
        {
            /* Perform the ISR */
            (*dma6_7Array[i].userISR) (dma6_7Array[i].arg);

            /* Reset the interrutp cause bit in the DMA cause register */
            DMA4_7_CAUSE_REG = ~(dma6_7Array[i].causeBit);
        }
}
#endif /* INCLUDE_DMA_4_7 */

/*******************************************************************************
* dmaErrorInt - DMA 0-7 Error interrupt controller routine.n
*
* DESCRIPTION:
*       This routine handles the DMA 0-7 Error interrupts. 
*       As soon as the interrupt signal is active the CPU analyzes the GT DMA 
*       0-3 Interrupt Cause register in order to locate the originating 
*       interrupt event. 
*       Then the routine calls the user specified service routine for that 
*       interrupt cause.
*       The routine does the same for DMA 4-7 Interrupt cause register.
*       The function first scans the dmaError0_3Array[] (dmaError0_3count valid 
*       entries) trying to find a hit and then it does the same for 
*       dmaError4_7Array. When found, the ISR in the same entry is executed.
*
* INPUT:
*       None.
*
* OUTPUT:
*       If a cause bit is active and it's connected to an ISR function,
*       the function will be called.
*
* RETURN:
*       None.
*
*******************************************************************************/
void dmaErrorInt (void)
{
    int     i;         
    unsigned int causeAndMask;

    /* Cause bit is active if an interrupt occured and the bit is unmasked. */
    causeAndMask = DMA0_3_CAUSE_REG & DMA0_3_MASK_REG ;

    for(i = 0; i < dmaError0_3Count; i++)
        if(causeAndMask & dmaError0_3Array[i].causeBit)
        {
            /* Perform the ISR */
            (*dmaError0_3Array[i].userISR) (dmaError0_3Array[i].arg);

            /* Reset the interrutp cause bit in the DMA cause register */
            DMA0_3_CAUSE_REG = ~(dmaError0_3Array[i].causeBit);
        }

#ifdef INCLUDE_DMA_4_7
	/* Cause bit is active if an interrupt occured and the bit is unmasked. */
    causeAndMask = DMA4_7_CAUSE_REG & DMA4_7_MASK_REG ;

    for(i = 0; i < dmaError4_7Count; i++)
        if(causeAndMask & dmaError4_7Array[i].causeBit)
        {
            /* Perform the ISR */
            (*dmaError4_7Array[i].userISR) (dmaError4_7Array[i].arg);

            /* Reset the interrutp cause bit in the DMA cause register */
            DMA4_7_CAUSE_REG = ~(dmaError4_7Array[i].causeBit);
        }
#endif
}