sil3124drv.h

来自「Curtiss-Wright Controls Embedded Computi」· C头文件 代码 · 共 313 行

/**************************************************************************
 *
 *   Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights
 *   reserved.  This Source Code is the Property of Curtiss-Wright
 *   Controls, Inc. and can only be used in accordance with Source
 *   Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any
 *   of its subsidiaries.
 *
 **************************************************************************/

/*FILE HEADER**************************************************************
 * Product Name:
 *
 * File %name:    sil3124Drv.h %
 * Instance:      kanata_1
 *
 * Description: SATA disk controller header
 *
 * This file contains all SATA definitions, and SIL3124 registers, data
 * structures, etc.
 *
 * %created_by:   dle %
 * %date_created: Mon Nov 14 13:05:30 2005 %
 *
 * Notes:
 *
 * History:
 *
 *END FILE HEADER*********************************************************/
#ifndef _kanata_1_sil3124Drv_h_H
#define _kanata_1_sil3124Drv_h_H

#ifdef __cplusplus
extern "C" {
#endif

#include "private/semLibP.h"
#include "blkIo.h"

#define SIL3124_MAX_PORTS          4
#define SIL3124_MAX_DRIVES         1
#define SIL3124_SLOT_SIZE          128
#define SIL3124_IRS1_PORT_SIZE     0x2000
#define SIL3124_SEM_TIMEOUT_DEF    3 /* seconds */

/* ATA macros */

#define ATA_MAX_PRD                256
#define ATA_SECT_SIZE              512

#define ATA_ID_WORDS               256
#define ATA_ID_VALID               53
#define ATA_ID_CUR_HEADS           55
#define ATA_ID_CUR_SECT_PER_TRK    56
#define ATA_ID_UDMA_MODES          88

#define ATA_CMD_READ               0xC8
#define ATA_CMD_READ_EXT           0x25
#define ATA_CMD_WRITE              0xCA
#define ATA_CMD_WRITE_EXT          0x35
#define ATA_CMD_ID_ATA             0xEC
#define ATA_CMD_SET_FEATURES       0xEF

#define SETFEATURES_XFER           0x03
#define XFER_UDMA_0                0x40

enum {
   /* bits in ATA command block registers */
   ATA_HOB                 = (1 << 7),     /* LBA48 selector */
   ATA_NIEN                = (1 << 1),     /* disable-irq flag */
   ATA_LBA                 = (1 << 6),     /* LBA28 selector */
   ATA_DEV1                = (1 << 4),     /* Select Device 1 (slave) */
   ATA_DEVICE_OBS          = (1 << 7) | (1 << 5), /* obs bits in dev reg */
   ATA_DEVCTL_OBS          = (1 << 3),     /* obsolete bit in devctl reg */
   ATA_BUSY                = (1 << 7),     /* BSY status bit */
   ATA_DRDY                = (1 << 6),     /* device ready */
   ATA_DF                  = (1 << 5),     /* device fault */
   ATA_DRQ                 = (1 << 3),     /* data request i/o */
   ATA_ERR                 = (1 << 0),     /* have an error */
   ATA_SRST                = (1 << 2),     /* software reset */
   ATA_ABORTED             = (1 << 2),     /* command aborted */
};

#define ATA_OK(status) \
((status & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ | ATA_ERR)) == ATA_DRDY)

/* global control register definitions */

#define SIL3124_IRS0_GC_GLOBAL_RESET    (1<<31)
#define SIL3124_IRS0_GC_PORT3_ENABLE    (1<<3)
#define SIL3124_IRS0_GC_PORT2_ENABLE    (1<<2)
#define SIL3124_IRS0_GC_PORT1_ENABLE    (1<<1)
#define SIL3124_IRS0_GC_PORT0_ENABLE    (1<<0)

/* port interrupt status register definitions */

#define SIL3124_IRS1_IS_SDB_NOTIFY      (1<<11)
#define SIL3124_IRS1_IS_HS_ERR_TH       (1<<10)
#define SIL3124_IRS1_IS_CRC_ERR_ETH     (1<<9)
#define SIL3124_IRS1_IS_BD_ERR_ETH      (1<<8)
#define SIL3124_IRS1_IS_DEV_EXCHG       (1<<7)
#define SIL3124_IRS1_IS_UNREC_FIS       (1<<6)
#define SIL3124_IRS1_IS_COM_WAKE        (1<<5)
#define SIL3124_IRS1_IS_PHY_RDY_CHG     (1<<4)
#define SIL3124_IRS1_IS_PM_CHG          (1<<3)
#define SIL3124_IRS1_IS_PORT_READY      (1<<2)
#define SIL3124_IRS1_IS_CMD_ERROR       (1<<1)
#define SIL3124_IRS1_IS_CMD_CMPL        (1<<0)

/* interrupt mask definitions */

#define SIL3124_INT_MASK_ALL    \
(\
   SIL3124_IRS0_GC_PORT0_ENABLE|\
   SIL3124_IRS0_GC_PORT1_ENABLE|\
   SIL3124_IRS0_GC_PORT2_ENABLE|\
   SIL3124_IRS0_GC_PORT3_ENABLE\
)

#define SIL3124_INT_PORT_ALL    \
(\
   SIL3124_IRS1_IS_SDB_NOTIFY|\
   SIL3124_IRS1_IS_HS_ERR_TH|\
   SIL3124_IRS1_IS_CRC_ERR_ETH|\
   SIL3124_IRS1_IS_BD_ERR_ETH|\
   SIL3124_IRS1_IS_DEV_EXCHG|\
   SIL3124_IRS1_IS_UNREC_FIS|\
   SIL3124_IRS1_IS_COM_WAKE|\
   SIL3124_IRS1_IS_PHY_RDY_CHG|\
   SIL3124_IRS1_IS_PM_CHG|\
   SIL3124_IRS1_IS_PORT_READY|\
   SIL3124_IRS1_IS_CMD_ERROR|\
   SIL3124_IRS1_IS_CMD_CMPL\
)

/* scatter/gather entry (sge) */

typedef struct sil3124_sge
{
   UINT32 dataAddrL;
   UINT32 dataAddrH;
   UINT32 dataCount;
   UINT32 dataCtrl;
} sil3124_sge_t;

/* data control word bit definitions */

#define SIL3124_SGE_DC_TRM       (1<<31)
#define SIL3124_SGE_DC_LNK       (1<<30)
#define SIL3124_SGE_DC_DRD       (1<<29)
#define SIL3124_SGE_DC_XCF       (1<<28)

/* port request block */

typedef struct sil3124_prb
{
   UINT32 control;               /* 00 */
   UINT32 rxTransferCount;       /* 04 */

   union
   {
      struct
      {
         UINT8 featuresErr;      /* 0b */
         UINT8 cmdStat;          /* 0a */
         UINT8 pmp;              /* 09 */
         UINT8 fisType;          /* 08 */
      } byte;
      struct
      {
         UINT32 data;
      } word;
   } word08;

   union
   {
      struct
      {
         UINT8 devHead;          /* 0f */
         UINT8 cylinderH;        /* 0e */
         UINT8 cylinderL;        /* 0d */
         UINT8 sectorNum;        /* 0c */
      } byte;
      struct
      {
         UINT32 data;
      } word;
   } word0c;

   union
   {
      struct
      {
         UINT8 devHeadExp;       /* 13 */
         UINT8 cylinderHExp;     /* 12 */
         UINT8 cylinderLExp;     /* 11 */
         UINT8 sectorNumExp;     /* 10 */
      } byte;
      struct
      {
         UINT32 data;
      } word;
   } word10;

   union
   {
      struct
      {
         UINT8 devCtrl;          /* 17 */
         UINT8 reserved16;       /* 16 */
         UINT8 sectorCntExp;     /* 15 */
         UINT8 sectorCnt;        /* 14 */
      } byte;
      struct
      {
         UINT32 data;
      } word;
   } word14;

   UINT32 reserved18;            /* 18 */
   UINT32 reserved1c;            /* 1c */

   sil3124_sge_t sges[2];        /* 20 - scatter/gather table */
} SIL3124_PRB;

#define SIL3124_PRB_CONTROL_C_SOFTRESET (1<<7)
#define SIL3124_PRB_FIS_TYPE_RHD        0x27   /* register - host to device */
#define SIL3124_PRB_PMP_CMD             (1<<7) /* fis is a command */

/* internal register space 0 */

#define SIL3124_IRS0_GLOBAL_CTRL_REG    0x0040
#define SIL3124_IRS0_GLOBAL_INTSTAT_REG 0x0044

/* internal register space 1 */

#define SIL3124_IRS1_CTRL_STAT_REG      0x1000
#define SIL3124_IRS1_CTRL_CLR_REG       0x1004
#define SIL3124_IRS1_INT_STAT_REG       0x1008
#define SIL3124_IRS1_INT_ENA_SET_REG    0x1010
#define SIL3124_IRS1_ACT_UPPER_ADR_REG  0x101c
#define SIL3124_IRS1_CMD_EXE_FIFO_REG   0x1020
#define SIL3124_IRS1_CMD_ERR_REG        0x1024
#define SIL3124_IRS1_SLOT_STAT_REG      0x1800
#define SIL3124_IRS1_SSTATUS_REG        0x1f04

/* port control status register definitions */
#define SIL3124_IRS1_PS_PORT_READY      (1<<31)
#define SIL3124_IRS1_PCS_32BA           (1<<10)
#define SIL3124_IRS1_PCS_INOCLRONREAD   (1<<3)

/* port clear register definitions */
#define SIL3124_IRS1_PC_PORT_RESET      (1<<0)

/* port interrupt enable set/clear register definitions */
#define SIL3124_IRS1_IE_CMD_ERROR       (1<<1)
#define SIL3124_IRS1_IE_CMD_CMPL        (1<<0)

/* port sstatus register definitions */
#define SIL3124_IRS1_SSTATUS_DET_MASK   0xf
#define SIL3124_IRS1_SSTATUS_DET_OKAY   0x3

typedef struct sil3124_Dev
{
   BLK_DEV     blkDev;         /* must be here */
   int         port;           /* port no. 0 - 3 */
   int         blkOffset;      /* sector offset */
} SIL3124_DEV;

typedef struct sil3124_Port {
   int devPresent;             /* device present mask */
   int semTimeout;             /* timeout seconds for sync sema */
   SEMAPHORE syncSem;          /* sema for synchronization */
   SEMAPHORE muteSem;          /* sema for mutual exclusion */
   UINT16 idDev[ATA_ID_WORDS]; /* identify device data */
   UINT32 dmaBuf;              /* buffer for command data */
} SIL3124_PORT;

typedef struct sil3124_Ctrl {
   UINT32 irs0;     /* internal register space 0 */
   UINT32 irs1;     /* internal register space 1 */
   SIL3124_PORT port[SIL3124_MAX_PORTS];
} SIL3124_CTRL;

/* function declarations */

#if defined(__STDC__) || defined(__cplusplus)

extern STATUS  sil3124Drv       (void);
extern BLK_DEV *sil3124DevCreate(int port, int drive, int nBlks, int offset);
extern void    sil3124CtrlInit  (UINT32 irs0, UINT32 irs1, int portConfig);
extern void    sysSataIntEnable (void);
extern void    sysSataIntConnect(VOIDFUNCPTR rtn, int arg);

#else

extern STATUS  sil3124Drv       ();
extern BLK_DEV *sil3124DevCreate();
extern void    sil3124CtrlInit  ();
extern void    sysSataIntEnable ();
extern void    sysSataIntConnect();

#endif  /* __STDC__ */


#ifdef __cplusplus
}
#endif

#endif /* kanata_1_sil3124Drv_h_H */

/* END OF FILE */