fwcard_fwx.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/**********************************************************************
 *
 *   Copyright (c) 2004, Dy 4 Systems All rights reserved.
 *   This Source Code is the Property of Dy 4 Systems Inc. and
 *   can only be used in accordance with Source Code License
 *   Agreement of Dy 4 Systems Inc. dba (doing business as) 
 *   CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING, "CWCEC". 
 *
 **********************************************************************/

/*FILE HEADER*****************************************************************
 *   
 *  %name:          fwCard_fwx.h %
 *
 *  Description:    Contains card (SBC) specific definitions for BIT results 
 *
 *  %created_by:    rdriscol %
 *  %date_created:   Tue Oct 12 16:37:55 2004 %
 * 
 *  Notes:
 *          
 *  History:
 *     01c, 18jul05, tis - updated based on the fwx file fwCard.h version fwcard_v14
 *     01b, 10nov04, tis - updated based on the fwx file fwCard.h version 28
 *     01a, 30sep04, tis - created based on the fwx file fwCard.h version 27
 *                       - Removed typedef (*VOIDFUNCPTR)()
 *                       - Added typedef BOOLEAN
 *END FILE HEADER************************************************************/

#ifndef _FW_CARD_H
#define _FW_CARD_H

/*---------------------------------------------------------------------------*/
/* compiler switches */
#ifdef __cplusplus
extern "C"
{
#endif

/*---------------------------------------------------------------------------*/
/* Constants */

#define END_32BIT_REG_TABLE  0xffffffff

/* CPU numbers for multi-processor cards */
#define FW_CPU_NUM_0       0
#define FW_CPU_NUM_1       1
#define FW_CPU_NUM_2       2
#define FW_CPU_NUM_3       3
#define FW_CPU_NUM_4       4
#define FW_CPU_NUM_5       5
#define FW_CPU_NUM_6       6
#define FW_CPU_NUM_7       7

#ifndef _ASMLANGUAGE
/* Device Record Table constants */
#define FW_MAX_DEVICE_RECORDS 128    /* maximum number of records allowed in device table */
#define FW_DEF_OWNER      0
#define FW_DEF_DEV_ADDR   NULL
#define FW_DEVICE_CLASS_MASK 0xFFFF0000  /* mask to extract the device class from the device handle */
#define FW_DEVICE_INDEX_MASK 0x0000FFFF  /* mask to extract the device index from the device handle */

/* BIT/DST constants */
#define FW_MAX_DIAGS             128 /* Maximum number of diagnostics */ 
#define FW_MAX_TEST_PARAMETERS   16  /* Maximum number of test parameters per device */
#define FW_MAX_DSM_BITS          32  /* Maximum number of BITs per DSM */  

/* General defines */
#define FW_MAX_NUM_CPU  2                /* Maximum number of CPUs supported in structures */

#ifndef NOT_APPLICABLE
#define NOT_APPLICABLE  0xFFFFFFFF       /* used if feature not to be used */
#endif
#define HANDLE_SPACING    0x20

typedef unsigned int   BOOLEAN;

/**********************************************************************
* Device type definitions
**********************************************************************/
/* Device Class type definitions */
typedef enum 
{
    FW_SERIAL_CLASS          = 0x00100000,   /* Serial devices */                      
    FW_USB_CLASS             = 0x00200000,   /* Universal Serial Buses */           
    FW_RTC_CLASS             = 0x00300000,   /* Real-time clocks */
    FW_TIMER_CLASS           = 0x00400000,   /* timers/counters */
    FW_FLASH_CLASS           = 0x00500000,   /* flash banks */
    FW_L_CACHE_CLASS         = 0x00600000,   /* L2/L3 cache banks */
    FW_RAM_CLASS             = 0x00700000,   /* RAM/NOVRAM banks */
    FW_SEEPROM_CLASS         = 0x00800000,   /* serial eeprom banks */
    FW_SCSI_CLASS            = 0x00900000,   /* SCSI devices */
    FW_ETHERNET_CLASS        = 0x00A00000,   /* Ethernet devices */
    FW_VMEBUS_CLASS          = 0x00B00000,   /* VME BUS devices */
    FW_FPGA_CLASS            = 0x00C00000,   /* Board controller fpga devices */
    FW_WATCHDOG_CLASS        = 0x00D00000,   /* Hardware watchdogs */
    FW_CPU_CLASS             = 0x00E00000,   /* CPU processors */ 
    FW_CARD_CONTROLLER_CLASS = 0x00F00000,   /* Card controllers (North Bridges) */
    FW_BRIDGE_CLASS          = 0x01000000,   /* bridges (i.e. PCI) */
    FW_DMA_CONTROLLER_CLASS  = 0x01100000,   /* general-purpose DMA controllers */
    FW_PHY_CLASS             = 0x01200000,   /* phyceiver devices */
    FW_1553_CLASS            = 0x01400000,   /* 1553 devices */
    FW_TUNNEL_CLASS          = 0x01500000,   /* Tunnel devices */
    FW_GPU_CLASS             = 0x01600000,   /* Graphics Proc.  devices */
    FW_ECC_CLASS             = 0x01700000,   /* Error Correction Circuitry */
    FW_TEMP_SEN_CLASS        = 0x01800000,   /* Temperature Sensors */
    FW_PLL_CLASS             = 0x01900000,   /* PLL Clocks */
    FW_COMP_VIDEO_INP_CLASS  = 0x01A00000,   /* Composite video input devices */

    /* add more class types above this line */
    eFW_CLASS_TYPE_END

} eFW_CLASS_TYPE;
/* Device handle Definition */
typedef enum 
{
    FW_SERIAL_1         = FW_SERIAL_CLASS+1,
    FW_SERIAL_2         = FW_SERIAL_CLASS+2,
    FW_SERIAL_3         = FW_SERIAL_CLASS+3,
    FW_SERIAL_4         = FW_SERIAL_CLASS+4,
    FW_SERIAL_5         = FW_SERIAL_CLASS+5,
    FW_SERIAL_6         = FW_SERIAL_CLASS+6,
    FW_SERIAL_7         = FW_SERIAL_CLASS+7,
    FW_SERIAL_8         = FW_SERIAL_CLASS+8,
    FW_SERIAL_9         = FW_SERIAL_CLASS+9,
    FW_SERIAL_10        = FW_SERIAL_CLASS+10,
    FW_SERIAL_11        = FW_SERIAL_CLASS+11,
    FW_SERIAL_12        = FW_SERIAL_CLASS+12,
    FW_SERIAL_13        = FW_SERIAL_CLASS+13,

    FW_USB_1            = FW_USB_CLASS+1,
    FW_USB_2            = FW_USB_CLASS+2,
    FW_USB_3            = FW_USB_CLASS+3,

    FW_RTC_1            = FW_RTC_CLASS+1,

    FW_TIMER_1          = FW_TIMER_CLASS+1,
    FW_TIMER_2          = FW_TIMER_CLASS+2,
    FW_TIMER_3          = FW_TIMER_CLASS+3,
    FW_TIMER_4          = FW_TIMER_CLASS+4,
    FW_TIMER_5          = FW_TIMER_CLASS+5,
    FW_TIMER_6          = FW_TIMER_CLASS+6,
    FW_GENERAL_PURPOSE_TIMER_1 = FW_TIMER_CLASS+HANDLE_SPACING+1,
    FW_GENERAL_PURPOSE_TIMER_2 = FW_TIMER_CLASS+HANDLE_SPACING+2,
    FW_GENERAL_PURPOSE_TIMER_3 = FW_TIMER_CLASS+HANDLE_SPACING+3,
    FW_GENERAL_PURPOSE_TIMER_4 = FW_TIMER_CLASS+HANDLE_SPACING+4,
    FW_GENERAL_PURPOSE_TIMER_5 = FW_TIMER_CLASS+HANDLE_SPACING+5,
    FW_GENERAL_PURPOSE_TIMER_6 = FW_TIMER_CLASS+HANDLE_SPACING+6,
    FW_GENERAL_PURPOSE_TIMER_7 = FW_TIMER_CLASS+HANDLE_SPACING+7,
    FW_GENERAL_PURPOSE_TIMER_8 = FW_TIMER_CLASS+HANDLE_SPACING+8,

    FW_L2_CACHE_SRAM_1  = FW_L_CACHE_CLASS+1,
    FW_L3_CACHE_SRAM_1  = FW_L_CACHE_CLASS+HANDLE_SPACING+1,
    FW_L3_CACHE_SRAM_2  = FW_L_CACHE_CLASS+HANDLE_SPACING+2,

    FW_SDRAM_1          = FW_RAM_CLASS+1,
    FW_SDRAM_2          = FW_RAM_CLASS+2,
    FW_NOVRAM_1         = FW_RAM_CLASS+HANDLE_SPACING+1,
    FW_ISRAM_1          = FW_RAM_CLASS+(2*HANDLE_SPACING)+1,

    FW_FLASH_BANK_1     = FW_FLASH_CLASS+1,
    FW_FLASH_BANK_2     = FW_FLASH_CLASS+2,
    FW_FLASH_BANK_3     = FW_FLASH_CLASS+3,
    FW_FLASH_BANK_4     = FW_FLASH_CLASS+4,
    FW_PABS_1           = FW_FLASH_CLASS+HANDLE_SPACING+1,
    FW_PABS_2           = FW_FLASH_CLASS+HANDLE_SPACING+2,
    FW_FLASH_ISP_1      = FW_FLASH_CLASS+(2*HANDLE_SPACING)+1,

    FW_SEEPROM_1        = FW_SEEPROM_CLASS+1,
    FW_SEEPROM_2        = FW_SEEPROM_CLASS+2,

    FW_SCSI_1           = FW_SCSI_CLASS+1,

    FW_ETHERNET_1       = FW_ETHERNET_CLASS+1,
    FW_ETHERNET_2       = FW_ETHERNET_CLASS+2,
    FW_ETHERNET_3       = FW_ETHERNET_CLASS+3,

    FW_VMEBUS           = FW_VMEBUS_CLASS+1,

    FW_FPGA_1           = FW_FPGA_CLASS+1,
    FW_FPGA_2           = FW_FPGA_CLASS+2,

    FW_WATCHDOG_1       = FW_WATCHDOG_CLASS+1,
    FW_WATCHDOG_2       = FW_WATCHDOG_CLASS+2,

    FW_CPU_0            = FW_CPU_CLASS+1,
    FW_CPU_1            = FW_CPU_CLASS+2,

    FW_CARD_CONTROLLER_1= FW_CARD_CONTROLLER_CLASS+1,

    FW_PCI_BRIDGE_1     = FW_BRIDGE_CLASS+1,
    FW_PCI_BRIDGE_2     = FW_BRIDGE_CLASS+2,

    FW_DMA_CONTROLLER_1 = FW_DMA_CONTROLLER_CLASS+1,
    FW_DMA_CONTROLLER_2 = FW_DMA_CONTROLLER_CLASS+2,
    FW_DMA_CONTROLLER_3 = FW_DMA_CONTROLLER_CLASS+3,
    FW_DMA_CONTROLLER_4 = FW_DMA_CONTROLLER_CLASS+4,
    FW_DMA_CONTROLLER_5 = FW_DMA_CONTROLLER_CLASS+5,
    FW_DMA_CONTROLLER_6 = FW_DMA_CONTROLLER_CLASS+6,
    FW_DMA_CONTROLLER_7 = FW_DMA_CONTROLLER_CLASS+7,
    FW_DMA_CONTROLLER_8 = FW_DMA_CONTROLLER_CLASS+8,

    FW_PHY_1            = FW_PHY_CLASS+1,
    FW_PHY_2            = FW_PHY_CLASS+2,
    FW_PHY_3            = FW_PHY_CLASS+3,

    FW_1553_1           = FW_1553_CLASS+1,

    FW_TUNNEL_1         = FW_TUNNEL_CLASS+1,

    FW_GPU_1            = FW_GPU_CLASS+1,
    FW_GPU_2            = FW_GPU_CLASS+2,

    FW_ECC_1            = FW_ECC_CLASS+1,
    FW_ECC_2            = FW_ECC_CLASS+2,

    FW_PLL_1            = FW_PLL_CLASS+1,

    FW_COMP_VIDEO_INP_1 = FW_COMP_VIDEO_INP_CLASS+1,

    /* add more device handles above this line */
    /* Do not add any handles after this line */
    eFW_PMC_DEVICES_BEGIN = 0x7FFE0000,
    eFW_DEVICE_HANDLE_END = 0x7FFF0000

} eFW_DEVICE_HANDLE;

/* Device Status Definition */
typedef enum 
{
    FW_DEVICE_DEACTIVATED,  /* device is deactivated */
    FW_DEVICE_UNINITIALIZED,/* device is present but uninitialized        */
    FW_DEVICE_OK,           /* device is mapped and ready to go      */
    FW_DEVICE_OK_INIT,      /* device is mapped,initialized, and ready to go */
    FW_DEVICE_DEGRADED,     /* device encountered service-affecting errors*/
    FW_DEVICE_ERROR,        /* device encountered fatal errors            */
    FW_DEVICE_NOT_PRESENT,  /* device is not present */

    /* add more device state above this line */
    eFW_DEVICE_STATE_END

} eFW_DEVICE_STATE;

/**********************************************************************
* Device Table entry structure
**********************************************************************/
typedef struct 
{
    eFW_DEVICE_HANDLE deviceHandle;   /* Device handle ID */
    void          *pDeviceAddress;    /* device base memory */
    eFW_DEVICE_STATE deviceStatus;    /* current status of device */
    UINT32        deviceOwner;        /* current owner of device */
    UINT8         primaryReg;         /* index of device primary register (BAR # for PCI) */
    UINT8         busId;              /* identification of bus type (see FW_BUS_ID_... labels) */
    UINT16        busDeviceIndex;     /* index for device on bus (0xFFFF = find index) */
    void          *pDeviceSpecData;   /* device specific information */
    UINT32        busLocatorAddr;     /* address to locate device on bus (BCA for PCI)*/
    UINT32        reserved2;          /* reserved parameter to pad */
} sFW_DEVICE_RECORD;

/**********************************************************************
* Device specific information structures
**********************************************************************/
/* Device specific structure types */
typedef enum 
{
    FW_DEVICE_SPEC_MEMORY,         /* memory device type */
    FW_DEVICE_SPEC_CCON,           /* card controller type */
    FW_DEVICE_SPEC_VMEBUS,         /* VMEBus type */
    FW_DEVICE_SPEC_CPU,            /* processor type */
    FW_DEVICE_SPEC_SERIAL,         /* serial port type */
    FW_DEVICE_SPEC_ETHERNET,       /* ethernet type */
    FW_DEVICE_SPEC_DMA_CONTROLLER, /* dma controller type */
    FW_DEVICE_SPEC_PHY,            /* phyceiver type */
    FW_DEVICE_SPEC_FPGA_TIMER,     /* FPGA timer */
    FW_DEVICE_SPEC_MPSC,           /* MPSC type */
    FW_DEVICE_SPEC_WATCHDOG,       /* Watchdog */
    FW_DEVICE_SPEC_FPGA,           /* FPGA */ 

    /* add more device specific types above this line */
    eFW_DEVICE_SPECIFIC_END

} eFW_DEVICE_SPECIFIC;

/* Memory devices specific information */
typedef struct 
{
    eFW_DEVICE_SPECIFIC devSpecType; /* type of device specific structure */
    UINT32    deviceSizeOfMemory; /* total memory for device */
    UINT16    compCount;          /* no. of components for device */
    UINT16    compBitWidth;       /* bit width of each component */
    UINT32    userRamFillAddr;    /* user RAM fill st addr */
    UINT32    userRamFillSize;    /* user RAM fill size in bytes */
    UINT32    userRamFillValue;   /* user RAM fill value */
    BOOLEAN   errorLogOn;         /* error logging allowed flag */
} sFW_DEVICE_MEMORY_INFO;


/* device test parameters structure */
typedef struct 
{
    UINT32        testParams[FW_MAX_TEST_PARAMETERS];
} sFW_TEST_PARAMS;

/* DST entry structure */
typedef struct {
    eFW_DEVICE_HANDLE eBitCode;  /* BIT diagnostic identifier code */
    BOOLEAN   testContOnFail;    /* sub-test continue-on-failure flag */
    UINT32    subTestMask;       /* sub-tests selector mask (bit position */
                                 /* is the test handle number) */ 
    sFW_TEST_PARAMS testParams;  /* test parameters for BIT function */
} sFW_DST_ENTRY;

typedef struct
{
 eFW_DEVICE_HANDLE eDevHandle;
 UINT8 devOwner;
} sFW_DEVICE_CPU_OWNER  ;
#endif /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* _FW_CARD_H */