pciext.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/**************************************************************************
 *
 *   Copyright (c) 2004, Dy 4 Systems All rights reserved.
 *   This Source Code is the Property of Dy 4 Systems Inc. and can
 *   only be used in accordance with Source Code License Agreement of
 *   Dy 4 Systems Inc. dba (doing business as) CURTISS-WRIGHT CONTROLS
 *   EMBEDDED COMPUTING, "CWCEC".
 *
 **************************************************************************/

/*FILE HEADER**********************************************************
 *
 *  Header %name:   pciExt.h %
 *  Instance:       kanata_1
 *
 *  Description:    Declaration of PCI functions available for general
 *                  use and definition for data structures and
 *                  constants used to pass data to/from these
 *                  functions.
 *
 *  %created_by:    jbrunsti %
 *  %date_created:  Tue Sep 07 15:05:11 2004 %
 *
 *  Notes:
 *
 *  History:
 *     13-Jul-2004  JB; Task 6848; CR 2086
 *                  Ported to FWX structure (See task 6848 for details)
 *     30-Aug-2004  JB; Task 6810; CR 2086
 *                  - removed "extern" from function declarations.
 *                  - modified function names to have "ss" prefix.
 *                  - added defines that equate previous function
 *                    names to the new function names.
 *                  - added declarations for ssPciConfigRead(...) &
 *                    ssPciConfigWrite(...).
 *      3-Sep-2004  JB; Task 6983; CR 2152
 *                  Added error code PCI_UNKNOWN_MEM_CNTRL_ID.
 *      7-Sep-2004  JB; Task 6992 (fix for task 6810); CR 2086
 *                  Add declaration for function ssPciService().
 *
 *END FILE HEADER*******************************************************/
#ifndef _kanata_1_pciExt_h_H
#define _kanata_1_pciExt_h_H


/*************************************************************************
 * PCI data structures and structure size macros:
 *************************************************************************/
#ifndef _ASMLANGUAGE

/*************************************************************************
 * NOTE to Dy 4 Software Developers making any future changes to the
 * following structures:
 *   - elements may not be removed or moved
 *   - only elements called "reserved" may be renamed
 *   - with the exception of re-naming a reserved field, all new
 *     elements must be added to the end of the data structure.
 *   - when the size of a structure is increased, a revision size
 *     define must be added and steps taken to ensure that all current
 *     and previous sizes of the structure are handled correctly and
 *     that PCI function calls using previous sizes will not be
 *     affected by the change.
 *************************************************************************/

/* Structure for data transfer during Hierarchy related operations */
typedef struct {
  UINT32   index;
  UINT32   baseBusNum;
  UINT32   highestSubBus;
  UINT32   *pConfAddrReg;
  UINT32   *pConfDataReg;
  UINT32  (*configRead)( UINT32 *pConfAddrReg, UINT32 *pConfDataReg,
                         UINT32 devBaseCnfgAddr,
                         UINT32 offset, UINT32 dataSize);
  UINT32  (*configWrite)( UINT32 *pConfAddrReg, UINT32 *pConfDataReg,
                          UINT32 devBaseCnfgAddr, 
                          UINT32 offset,
                          UINT32 writeData, UINT32 dataSize);
  UINT32   reserved;  /* make struct size a multiple of 4 32-bit words */
} pciHierarchyDataStruct;


#define PCI_HIER_BUF_SIZE  sizeof(pciHierarchyDataStruct)
#define PCI_HIER_BUF_REV_O_SIZE (8 * sizeof(UINT32))

/* Structures for data transfer during device related operations */
/************************************************************************
 * Overlays structure for data formatted exactly as found in the PCI
 * Configuration header: matches PCI spec 2.2.
 ************************************************************************/
typedef struct {
  UINT16   deviceId;
  UINT16   vendorId;
  UINT16   statReg;
  UINT16   cmdReg;
  UINT8    baseClass;
  UINT8    subClass;
  UINT8    progIf;
  UINT8    revisionId;
  UINT8    BIST;
  UINT8    headerType;
  UINT8    latTimer;
  UINT8    cacheSize;
  UINT32   bar[6];                  /* type zero header has 6 BARs */
  UINT32   cardBusCidPtr;
  UINT16   subSysId;
  UINT16   subVendorId;
  UINT32   expansionRom;
  UINT16   reserved1;
  UINT8    reserved2;
  UINT8    capabilitiesPtr;
  UINT32   reserved3;
  UINT8    maxLat;
  UINT8    minGnt;
  UINT8    intPin;
  UINT8    intLine;
} pciTypeZeroHdrStruct;
  

typedef struct {
  UINT16   deviceId;
  UINT16   vendorId;
  UINT16   statReg;
  UINT16   cmdReg;
  UINT8    baseClass;
  UINT8    subClass;
  UINT8    progIf;
  UINT8    revisionId;
  UINT8    BIST;
  UINT8    headerType;
  UINT8    latTimer;
  UINT8    cacheSize;
  UINT32   bar[2];                  /* type one header has 2 BARs */
  UINT8    secondaryLatTimer;
  UINT8    subordinateBusNum;
  UINT8    secondaryBusNum;
  UINT8    primaryBusNum;
  UINT16   secondaryStatus;
  UINT8    ioLimit;
  UINT8    ioBase;
  UINT16   memLimit;
  UINT16   memBase;
  UINT16   prefetchLimit;
  UINT16   prefetchBase;
  UINT32   prefBaseUpper32;
  UINT32   prefLimitUpper32;
  UINT16   ioLimitUpper16;
  UINT16   ioBaseUpper16;
  UINT16   reserved1;
  UINT8    reserved2;
  UINT8    capabilitiesPtr;
  UINT32   expansionRom;
  UINT16   bridgeControl;
  UINT8    intPin;
  UINT8    intLine;
} pciTypeOneHdrStruct;
  
typedef union {
  pciTypeZeroHdrStruct zero;
  pciTypeOneHdrStruct  one;
  UINT32                   reg32Bit[16];
} pciConfigHeaderUnion;

typedef struct {
  UINT32                   index;
  UINT32                   baseConfigAddr;
  UINT8                    reserved1;
  UINT8                    reserved2;
  UINT8                    reserved3;
  UINT8                    rw_header;
  UINT32                   reserved4;
  pciConfigHeaderUnion ty;
} pciDeviceDataStruct;

#define PCI_MIN_DEV_BUF_SIZE (4 * sizeof(UINT32)) /* index to reserved4 */
#define PCI_DEVICE_BUF_SIZE  sizeof(pciDeviceDataStruct)
#define PCI_DEVICE_BUF_REV_O_SIZE (20 * sizeof(UINT32))


typedef struct {
  UINT32                   index;
  UINT32                   reserved;
  UINT32                   bar[6]; /* max. 6 BARS in PCI Config. Space */
} pciBarSizeDataStruct;

#define PCI_BAR_SIZE_BUF_SIZE  sizeof(pciBarSizeDataStruct)
#define PCI_BAR_SIZE_BUF_REV_O_SIZE (8 * sizeof(UINT32))

/************************************************************************
 * NOTEs for the following data structure:
 *
 *  - The FF/W PCI specific code supports both contiguous and
 *    non-contiguous allocation of PCI memory space and I/O space for
 *    devices directly connected to PCI bus zero. FF/W only supports
 *    contiguous allocations on all other buses on the secondary side
 *    of PCI-to-PCI Bridge.
 *
 *  - FF/W PCI specific code also supports either starting at bottom
 *    or at the top of available Memory or I/O space when allocating
 *    space to each of the BARs.
 *
 ************************************************************************/
typedef struct {
  UINT32    hierarcyNum;
  UINT8     memKeepBus0Contiguous;
  UINT8     memAllocateUp;
  UINT8     ioKeepBus0Contiguous;
  UINT8     ioAllocateUp;
  UINT32    firstDeviceIndex;
  UINT32    lastDeviceIndex;
  UINT32    memBaseU32;  /* currently not used; available for future use */
  UINT32    memBaseL32;
  UINT32    memNextAddrL32;
  UINT32    memLimitL32;
  UINT32    ioBaseU32;  /* currently not used; available for future use */
  UINT32    ioBaseL32;
  UINT32    ioNextAddrL32;
  UINT32    ioLimitL32;
} pciSpaceAllocateStruct;


#define PCI_SPACE_DATA_BUF_SIZE  sizeof(pciSpaceAllocateStruct)
#define PCI_SPACE_DATE_BUF_REV_O_SIZE (12 * sizeof(UINT32))

#endif  /* #ifndef _ASMLANGUAGE */

/********************************************************************
 * PCI ERROR CODES
 *
 * NOTE that for backwards compatibilty the defines below match
 * defines found in css.h~22 as follows:
 *   - PCI_DEV_NOT_FOUND matches CSS_DEV_NOT_FOUND
 *   - error codes 200, 201 and 210 to 217 exactly match error codes
 *     that have a CSS_ prefix to names found below.
 ********************************************************************/
#define PCI_DEV_NOT_FOUND 0xFFFFFFFF

/* PCI Scan and device setup error codes */
#define PCI_DB_TOO_SMALL                ((UINT32)200)
#define PCI_CLASS_N_TYPE_MISMATCH       ((UINT32)201)

/* PCI service related error codes */
#define PCI_INVALID_SERVICE_CODE        ((UINT32)210)
#define PCI_SERVICE_CODE_UNIMPLEMENTED  ((UINT32)211)
#define PCI_INVALID_BUFFER_SIZE         ((UINT32)212)
#define PCI_DEVICE_COUNT_AT_MAX         ((UINT32)213)
#define PCI_INVALID_DEVICE_INDEX        ((UINT32)214)
#define PCI_HIERARCHY_COUNT_AT_MAX      ((UINT32)215)
#define PCI_INVALID_HIERARCHY_INDEX     ((UINT32)216)
#define PCI_DEVICE_DATA_MISMATCH        ((UINT32)217)

#define PCI_NOT_INITIALIZED_FOR_USE     ((UINT32)218)
#define PCI_INPUT_VALUE_GT_MAX          ((UINT32)219)
#define PCI_DATA_SIZE_N_OFFSET_MISMATCH ((UINT32)220)
#define PCI_INVALID_DATA_SIZE           ((UINT32)221)
#define PCI_INVALID_BASE_CONFIG_ADDRESS ((UINT32)222)
#define PCI_UNKNOWN_MEM_CNTRL_ID         ((UINT32)223)


/*************************************************************************
 * PCI service op codes (values 0x01 to 0x0f exactly match same codes
 * in css.h~22 that have "CSS" prefix instead of "PCI"):
 *************************************************************************/
#define   PCI_ADD_PCI_HIERARCHY       0x01
#define   PCI_SET_PCI_HIERARCHY       0x02
#define   PCI_GET_PCI_HIERARCHY       0x03
#define   PCI_GET_LAST_PCI_HIERARCHY  0x04
#define   PCI_DETECT_PCI_DEVICE       0x05
#define   PCI_SET_PCI_DEVICE          0x06
#define   PCI_GET_PCI_DEVICE          0x07
#define   PCI_GET_LAST_PCI_DEVICE     0x08
#define   PCI_FIND_PCI_DEVICE         0x09
#define   PCI_PROGRAM_PCI_DEVICE      0x0a
#define   PCI_GET_PCI_BAR_SIZE        0x0b
#define   PCI_BUS_ENUMERATION         0x0c
#define   PCI_DEFINE_MAP              0x0d
#define   PCI_PROGRAM_DEVICES         0x0e
#define   PCI_SETUP_HIERARCHY         0x0f


/*********************************************************************
 * Declarations for PCI functions that are available for general use.
 *
 *  Note that two two APIs are now supported for PCI configuration
 *  space read and write operations. The newest API for each expects
 *  the bus, device and function number of the PCI device to be
 *  read/writen to be provided in one 32 bit input argument.  The
 *  other API for read and for write expects the historic method of
 *  individual input arguments for the bus, device and functions
 *  numbers.
 *********************************************************************/
UINT32 ssPciGetError();

UINT32 ssPciLocalInit(void *infoTable);

UINT32 ssPciConfigRead( UINT32 cnfgAddrbusNo,
                        UINT32 offset,
                        UINT32 dataSize );

UINT32 ssPciConfigWrite( UINT32 cnfgAddrbusNo,
                         UINT32 offset,
                         UINT32 writeData,
                         UINT32 dataSize );

UINT32 ssPciCnfgRead( UINT32 busNo,
                      UINT32 deviceNo,
                      UINT32 funcNo,
                      UINT32 offset,
                      UINT32 dataSize );

UINT32 ssPciCnfgWrite( UINT32 busNo,
                       UINT32 deviceNo,
                       UINT32 funcNo,
                       UINT32 offset,
                       UINT32 writeData,
                       UINT32 dataSize );

UINT32 ssPciService( UINT32  opCode,
                     void    *pDataBuf,
                     UINT32  sizeOfBuf);

UINT32 ssPciMaxBusNo();


/********************************************************************
 * Defines that allow use of previous names of above functions. Note
 * that functions new to FWX are do not have defines included below.
 ********************************************************************/
#define pciGetError             ssPciGetError
#define pciLocalInitialization  ssPciLocalInit
#define pciCnfgRead             ssPciCnfgRead
#define pciCnfgWrite            ssPciCnfgWrite
#define pciService              ssPciService
#define pciMaxBusNo             ssPciMaxBusNo


/********************************************************************
 * NOTE that the following defines are expected to be removed from
 * this file as part the resolution of CR 2100.
 ********************************************************************/

/*#################*/
#ifndef COMPLETED_OK
#define COMPLETED_OK 0  /* same value as in dy4std.h used in FFW9 */
#endif
/*#################*/

/*#################*/
#ifndef NOT_APPLICABLE
#define NOT_APPLICABLE  (-1)  /* same value as in dy4std.h */
#endif
/*#################*/


#endif  /* #ifndef _kanata_1_pciExt_h_H */

/***** END OF FILE *****/