gt644xx.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

#define MPSC_CAUSE_REG(port)                                (0xb804 + ((port)<<3))
#define MPSC_MASK_REG(port)                                 (0xb884 + ((port)<<3))

#define MPSC_MAIN_CONFIG_LOW(port)                          (0x8000 + ((port)<<12))
#define MPSC_MAIN_CONFIG_HIGH(port)                         (0x8004 + ((port)<<12))
#define MPSC_PROTOCOL_CONFIG(port)                          (0x8008 + ((port)<<12))
#define MPSC_CHANNEL_REG1(port)                             (0x800c + ((port)<<12))
#define MPSC_CHANNEL_REG2(port)                             (0x8010 + ((port)<<12))
#define MPSC_CHANNEL_REG3(port)                             (0x8014 + ((port)<<12))
#define MPSC_CHANNEL_REG4(port)                             (0x8018 + ((port)<<12))
#define MPSC_CHANNEL_REG5(port)                             (0x801c + ((port)<<12))
#define MPSC_CHANNEL_REG6(port)                             (0x8020 + ((port)<<12))
#define MPSC_CHANNEL_REG7(port)                             (0x8024 + ((port)<<12))
#define MPSC_CHANNEL_REG8(port)                             (0x8028 + ((port)<<12))
#define MPSC_CHANNEL_REG9(port)                             (0x802c + ((port)<<12))
#define MPSC_CHANNEL_REG10(port)                            (0x8030 + ((port)<<12))

        /*  MPSC0 Registers      */


/***************************************/
/*          SDMA Registers             */
/***************************************/

#define SDMA_CONFIG_REG(channel)                            (0x4000 + ((channel)<<13))
#define SDMA_COMMAND_REG(channel)                           (0x4008 + ((channel)<<13))
#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)         (0x4810 + ((channel)<<13))
#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)         (0x4c10 + ((channel)<<13))
#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)           (0x4c14 + ((channel)<<13))

#define SDMA_CAUSE_REG                                      0xb800
#define SDMA_MASK_REG                                       0xb880

/* BRG Interrupts */


#define BRG_CONFIG_REG(brg)                                 (0xb200 + ((brg)<<3))
#define BRG_BAUDE_TUNING_REG(brg)                           (0xb204 + ((brg)<<3))
#define BRG_CAUSE_REG                                       0xb834
#define BRG_MASK_REG                                        0xb8b4

/****************************************/
/* DMA Channel Control					*/
/****************************************/

#define DMA_CHANNEL0_CONTROL 							    0x840
#define DMA_CHANNEL0_CONTROL_HIGH						    0x880
#define DMA_CHANNEL1_CONTROL 							    0x844
#define DMA_CHANNEL1_CONTROL_HIGH						    0x884
#define DMA_CHANNEL2_CONTROL 							    0x848
#define DMA_CHANNEL2_CONTROL_HIGH						    0x888
#define DMA_CHANNEL3_CONTROL 							    0x84C
#define DMA_CHANNEL3_CONTROL_HIGH						    0x88C


/****************************************/
/*           IDMA Registers             */
/****************************************/

#define DMA_CHANNEL0_BYTE_COUNT                             0x800
#define DMA_CHANNEL1_BYTE_COUNT                             0x804
#define DMA_CHANNEL2_BYTE_COUNT                             0x808
#define DMA_CHANNEL3_BYTE_COUNT                             0x80C
#define DMA_CHANNEL0_SOURCE_ADDR                            0x810
#define DMA_CHANNEL1_SOURCE_ADDR                            0x814
#define DMA_CHANNEL2_SOURCE_ADDR                            0x818
#define DMA_CHANNEL3_SOURCE_ADDR                            0x81c
#define DMA_CHANNEL0_DESTINATION_ADDR                       0x820
#define DMA_CHANNEL1_DESTINATION_ADDR                       0x824
#define DMA_CHANNEL2_DESTINATION_ADDR                       0x828
#define DMA_CHANNEL3_DESTINATION_ADDR                       0x82C
#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER                0x830
#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER                0x834
#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER                0x838
#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER                0x83C
#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER             0x870
#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER             0x874
#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER             0x878
#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER             0x87C

 /*  IDMA Address Decoding Base Address Registers  */

#define DMA_BASE_ADDR_REG0                                  0xa00
#define DMA_BASE_ADDR_REG1                                  0xa08
#define DMA_BASE_ADDR_REG2                                  0xa10
#define DMA_BASE_ADDR_REG3                                  0xa18
#define DMA_BASE_ADDR_REG4                                  0xa20
#define DMA_BASE_ADDR_REG5                                  0xa28
#define DMA_BASE_ADDR_REG6                                  0xa30
#define DMA_BASE_ADDR_REG7                                  0xa38

 /*  IDMA Address Decoding Size Address Register   */

#define DMA_SIZE_REG0                                       0xa04
#define DMA_SIZE_REG1                                       0xa0c
#define DMA_SIZE_REG2                                       0xa14
#define DMA_SIZE_REG3                                       0xa1c
#define DMA_SIZE_REG4                                       0xa24
#define DMA_SIZE_REG5                                       0xa2c
#define DMA_SIZE_REG6                                       0xa34
#define DMA_SIZE_REG7                                       0xa3C

 /* IDMA Address Decoding High Address Remap and Access
                  Protection Registers                    */

#define DMA_HIGH_ADDR_REMAP_REG0                            0xa60
#define DMA_HIGH_ADDR_REMAP_REG1                            0xa64
#define DMA_HIGH_ADDR_REMAP_REG2                            0xa68
#define DMA_HIGH_ADDR_REMAP_REG3                            0xa6C
#define DMA_BASE_ADDR_ENABLE_REG                            0xa80
#define DMA_CHANNEL0_ACCESS_PROTECTION_REG                  0xa70
#define DMA_CHANNEL1_ACCESS_PROTECTION_REG                  0xa74
#define DMA_CHANNEL2_ACCESS_PROTECTION_REG                  0xa78
#define DMA_CHANNEL3_ACCESS_PROTECTION_REG                  0xa7c
#define DMA_ARBITER_CONTROL                                 0x860
#define DMA_CROSS_BAR_TIMEOUT                               0x8d0

 /*  IDMA Headers Retarget Registers   */

#define DMA_HEADERS_RETARGET_CONTROL                        0xa84
#define DMA_HEADERS_RETARGET_BASE                           0xa88

 /*  IDMA Interrupt Register  */

#define DMA_INTERRUPT_CAUSE_REG                             0x8c0
#define DMA_INTERRUPT_MASK_REG                              0x8c4
          /* tissa- Added for 64360 backward compatibility */
#define DMA_INTERRUPT_CAUSE_MASK            DMA_INTERRUPT_MASK_REG
#define DMA_ERROR_ADDR                                      0x8c8
#define DMA_ERROR_SELECT                                    0x8cc

 /*  IDMA Debug Register ( for internal use )    */

#define DMA_DEBUG_LOW                                       0x8e0
#define DMA_DEBUG_HIGH                                      0x8e4
#define DMA_SPARE                                           0xA8C

/****************************************/
/* Timer_Counter 						*/
/****************************************/

#define TIMER_COUNTER0										0x850
#define TIMER_COUNTER1										0x854
#define TIMER_COUNTER2										0x858
#define TIMER_COUNTER3										0x85C
#define TIMER_COUNTER_0_3_CONTROL							0x864
#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE					0x868
#define TIMER_COUNTER_0_3_INTERRUPT_MASK      				0x86c

/****************************************/
/*         Watchdog registers     		*/
/****************************************/

#define WATCHDOG_CONFIG_REG                                 0xb410
#define WATCHDOG_VALUE_REG                                  0xb414

/****************************************/
/* I2C Registers                        */
/****************************************/

#define I2C_SLAVE_ADDR                                      0xc000
#define I2C_EXTENDED_SLAVE_ADDR                             0xc010
#define I2C_DATA                                            0xc004
#define I2C_CONTROL                                         0xc008
#define I2C_STATUS_BAUDE_RATE                               0xc00C
#define I2C_SOFT_RESET                                      0xc01c

/****************************************/
/* GPP Interface Registers              */
/****************************************/

#define GPP_IO_CONTROL                                      0xf100
#define GPP_LEVEL_CONTROL                                   0xf110
#define GPP_VALUE                                           0xf104
#define GPP_INTERRUPT_CAUSE                                 0xf108
#define GPP_INTERRUPT_MASK0                                 0xf10c
#define GPP_INTERRUPT_MASK1                                 0xf114
#define GPP_VALUE_SET                                       0xf118
#define GPP_VALUE_CLEAR                                     0xf11c

/****************************************/
/* Interrupt Controller Registers       */
/****************************************/

/****************************************/
/* Interrupts	  						*/
/****************************************/

#define MAIN_INTERRUPT_CAUSE_LOW                            0x004
#define MAIN_INTERRUPT_CAUSE_HIGH                           0x00c
#define CPU_INTERRUPT0_MASK_LOW                             0x014
#define CPU_INTERRUPT0_MASK_HIGH                            0x01c
#define CPU_INTERRUPT0_SELECT_CAUSE                         0x024
#define CPU_INTERRUPT1_MASK_LOW                             0x034
#define CPU_INTERRUPT1_MASK_HIGH                            0x03c
#define CPU_INTERRUPT1_SELECT_CAUSE                         0x044
#define INTERRUPT0_MASK_0_LOW                               0x054
#define INTERRUPT0_MASK_0_HIGH                              0x05c
#define INTERRUPT0_SELECT_CAUSE                             0x064
#define INTERRUPT1_MASK_0_LOW                               0x074
#define INTERRUPT1_MASK_0_HIGH                              0x07c
#define INTERRUPT1_SELECT_CAUSE                             0x084

/****************************************/
/*      MPP Interface Registers         */
/****************************************/

#define MPP_CONTROL0                                        0xf000
#define MPP_CONTROL1                                        0xf004
#define MPP_CONTROL2                                        0xf008
#define MPP_CONTROL3                                        0xf00c


#define MPP_DEBUG                                           0xf014     /* NEW */

/****************************************/
/*    Serial Initialization registers   */
/****************************************/

#define SERIAL_INIT_LAST_DATA                               0xf324
#define SERIAL_INIT_CONTROL                                 0xf328
#define SERIAL_INIT_STATUS                                  0xf32c


                                                            
/****************************************/
/*    FIFO Interface Registers          */
/****************************************/

#define FIFO_RX_SYNC_CONTROL0                               0x24a0
#define FIFO_RX_SYNC_CONTROL1                               0x28a0
#define FIFO_RX_SYNC_CONTROL2                               0x2ca0
#define FIFO_TX_SYNC_CONTROL0                               0x24a4
#define FIFO_TX_SYNC_CONTROL1                               0x28a4
#define FIFO_TX_SYNC_CONTROL2                               0x2ca4


                                                            
/*********************