gt644xx.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE         0x1C6C
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE        0x1C70
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE        0x1C74
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE        0x1CF8
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE        0x1CFC
#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE			        0x1C90
#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE  		        0x1C94
#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 		        0x1C98
#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE  		        0x1C9C
#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE  		        0x1CA0
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE  	        0x1CA4
#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	        0x1CA8
#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 		        0x1CAC
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE          0x1CB0
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE           0x1CB4
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE        0x1CC0
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE       0x1CC4
#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE 			        0x1CD0
#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 		            0x1CD4
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE        	0x1CE0
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE         0x1CE4
#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE         0x1CE8
#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE         0x1CEC
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE        0x1CF0
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE        0x1CF4
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE        0x1C78
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE        0x1C7C

/****************************************/
/*        Ethernet Unit Registers  		*/
/****************************************/

#define ETH_PHY_ADDR_REG                                     0x2000
#define ETH_SMI_REG                                          0x2004
#define ETH_UNIT_DEFAULT_ADDR_REG                            0x2008
#define ETH_UNIT_DEFAULTID_REG                               0x200c
#define ETH_UNIT_RESERVED                                    0x2014    /* NEW */
#define ETH_UNIT_INTERRUPT_CAUSE_REG                         0x2080
#define ETH_UNIT_INTERRUPT_MASK_REG                          0x2084
#define ETH_UNIT_INTERNAL_USE_REG                            0x24fc
#define ETH_UNIT_ERROR_ADDR_REG                              0x2094
#define ETH_UNIT_INTERNAL_ADDR_ERROR                         0x2098    /* NEW */ 
#define ETH_UNIT_PORTS_PADS_CALIB_0                          0x20A0    /* NEW */ 
#define ETH_UNIT_PORTS_PADS_CALIB_1                          0x20A4    /* NEW */ 
#define ETH_UNIT_PORTS_PADS_CALIB_2                          0x20A8    /* NEW */ 
#define ETH_UNIT_CONTROL                                     0x20B0    /* NEW */ 

#define ETH_WIN_BAR_REG(win)                                (0x2200 + ((win)<<3))
#define ETH_WIN_SIZE_REG(win)                               (0x2204 + ((win)<<3))
        /* tissa- Added for 64360 backward compatibility */
#define ETH_BAR_0                                            0x2200
#define ETH_BAR_1                                            0x2208
#define ETH_BAR_2                                            0x2210
#define ETH_BAR_3                                            0x2218
#define ETH_BAR_4                                            0x2220
#define ETH_BAR_5                                            0x2228
#define ETH_SIZE_REG_0                                       0x2204
#define ETH_SIZE_REG_1                                       0x220c
#define ETH_SIZE_REG_2                                       0x2214
#define ETH_SIZE_REG_3                                       0x221c
#define ETH_SIZE_REG_4                                       0x2224
#define ETH_SIZE_REG_5                                       0x222c


#define ETH_HEADERS_RETARGET_BASE_REG                        0x2230
#define ETH_HEADERS_RETARGET_CONTROL_REG                     0x2234

#define ETH_WIN_HIGH_ADDR_REMAP_REG(win)                    (0x2280 + ((win)<<2))
         /* tissa- Added for 64360 backward compatibility */
#define ETH_HIGH_ADDR_REMAP_REG_0                            0x2280
#define ETH_HIGH_ADDR_REMAP_REG_1                            0x2284
#define ETH_HIGH_ADDR_REMAP_REG_2                            0x2288
#define ETH_HIGH_ADDR_REMAP_REG_3                            0x228c


#define ETH_BASE_ADDR_ENABLE_REG                             0x2290
#define ETH_ACCESS_PROTECTION_REG(port)                     (0x2294 + ((port)<<2))
#define ETH_MIB_COUNTERS_BASE(port)                         (0x3000 + ((port)<<7))
#define ETH_PORT_CONFIG_REG(port)                           (0x2400 + ((port)<<10))
#define ETH_PORT_CONFIG_EXTEND_REG(port)                    (0x2404 + ((port)<<10))
#define ETH_MII_SERIAL_PARAMETRS_REG(port)                  (0x2408 + ((port)<<10))
#define ETH_GMII_SERIAL_PARAMETRS_REG(port)                 (0x240c + ((port)<<10))
#define ETH_VLAN_ETHERTYPE_REG(port)                        (0x2410 + ((port)<<10))
#define ETH_MAC_ADDR_LOW(port)                              (0x2414 + ((port)<<10))
#define ETH_MAC_ADDR_HIGH(port)                             (0x2418 + ((port)<<10))
#define ETH_SDMA_CONFIG_REG(port)                           (0x241c + ((port)<<10))
#define ETH_DSCP_0(port)                                    (0x2420 + ((port)<<10))
#define ETH_DSCP_1(port)                                    (0x2424 + ((port)<<10))
#define ETH_DSCP_2(port)                                    (0x2428 + ((port)<<10))
#define ETH_DSCP_3(port)                                    (0x242c + ((port)<<10))
#define ETH_DSCP_4(port)                                    (0x2430 + ((port)<<10))
#define ETH_DSCP_5(port)                                    (0x2434 + ((port)<<10))
#define ETH_DSCP_6(port)                                    (0x2438 + ((port)<<10))
#define ETH_PORT_SERIAL_CONTROL_REG(port)                   (0x243c + ((port)<<10))
#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)             (0x2440 + ((port)<<10))
#define ETH_PORT_STATUS_REG(port)                           (0x2444 + ((port)<<10))
#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)                (0x2448 + ((port)<<10))
#define ETH_TX_QUEUE_FIXED_PRIORITY(port)                   (0x244c + ((port)<<10))
#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)          (0x2450 + ((port)<<10))
#define ETH_MAXIMUM_TRANSMIT_UNIT(port)                     (0x2458 + ((port)<<10))
#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)            (0x245c + ((port)<<10))
#define ETH_INTERRUPT_CAUSE_REG(port)                       (0x2460 + ((port)<<10))
#define ETH_INTERRUPT_EXTEND_CAUSE_REG(port)                (0x2464 + ((port)<<10))
         /* tissa- Added for 64360 backward compatibility */
#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)                ETH_INTERRUPT_EXTEND_CAUSE_REG(port)


#define ETH_INTERRUPT_MASK_REG(port)                        (0x2468 + ((port)<<10))
#define ETH_INTERRUPT_EXTEND_MASK_REG(port)                 (0x246c + ((port)<<10))
#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)              (0x2470 + ((port)<<10))
#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)              (0x2474 + ((port)<<10))
#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)                 (0x247c + ((port)<<10))
#define ETH_RX_DISCARDED_FRAMES_COUNTER_REG(port)           (0x2484 + ((port)<<10)) 
         /* tissa- Added for 64360 backward compatibility */
#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)               ETH_RX_DISCARDED_FRAMES_COUNTER_REG(port)

#define ETH_RX_OVERRUN_FRAMES_COUNTER_REG(port)             (0x2488 + ((port)<<10))
#define ETH_PORT_DEBUG_0_REG(port)                          (0x248c + ((port)<<10))
#define ETH_PORT_DEBUG_1_REG(port)                          (0x2490 + ((port)<<10))
#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)              (0x2494 + ((port)<<10))
#define ETH_INTERNAL_USE_REG(port)                          (0x24fc + ((port)<<10))
#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)                 (0x2680 + ((port)<<10))
#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)                (0x2684 + ((port)<<10))

#define ETH_RX_CURRENT_QUEUE_DESC_PTR(port, queue)          (0x260c + ((port)<<10) + ((queue)<<4))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR(port, queue)          (0x26c0 + ((port)<<10) + ((queue)<<2))
         /* tissa- Added for 64360 backward compatibility */
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)              (0x260c + ((port)<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)              (0x261c + ((port)<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)              (0x262c + ((port)<<10))     
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)              (0x263c + ((port)<<10))     
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)              (0x264c + ((port)<<10))     
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)              (0x265c + ((port)<<10))     
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)              (0x266c + ((port)<<10))     
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)              (0x267c + ((port)<<10))     
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)              (0x26c0 + ((port)<<10))     
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)              (0x26c4 + ((port)<<10))     
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)              (0x26c8 + ((port)<<10))     
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)              (0x26cc + ((port)<<10))     
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)              (0x26d0 + ((port)<<10))     
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)              (0x26d4 + ((port)<<10))     
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)              (0x26d8 + ((port)<<10))     
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)              (0x26dc + ((port)<<10))     
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)            (0x2700 + ((port)<<10))
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)            (0x2710 + ((port)<<10))
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)            (0x2720 + ((port)<<10))
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)            (0x2730 + ((port)<<10))
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)            (0x2740 + ((port)<<10))
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)            (0x2750 + ((port)<<10))
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)            (0x2760 + ((port)<<10))
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)            (0x2770 + ((port)<<10))
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)           (0x2704 + ((port)<<10))
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)           (0x2714 + ((port)<<10))
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)           (0x2724 + ((port)<<10))
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)           (0x2734 + ((port)<<10))
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)           (0x2744 + ((port)<<10))
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)           (0x2754 + ((port)<<10))
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)           (0x2764 + ((port)<<10))
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)           (0x2774 + ((port)<<10))
#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)                (0x2708 + ((port)<<10))
#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)                (0x2718 + ((port)<<10))
#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)                (0x2728 + ((port)<<10))
#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)                (0x2738 + ((port)<<10))
#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)                (0x2748 + ((port)<<10))
#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)                (0x2758 + ((port)<<10))
#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)                (0x2768 + ((port)<<10))
#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)                (0x2778 + ((port)<<10))


#define ETH_TX_QUEUE_TOKEN_BUCKET_COUNT(port, queue)        (0x2700 + ((port)<<10) + ((queue)<<4))
#define ETH_TX_QUEUE_TOKEN_BUCKET_CONFIG(port, queue)       (0x2704 + ((port)<<10) + ((queue)<<4))
#define ETH_TX_QUEUE_ARBITER_CONFIG(port, queue)            (0x2708 + ((port)<<10) + ((queue)<<4))

#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)                (0x2780 + ((port)<<10))

#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)    (0x3400 + ((port)<<10))
#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)      (0x3500 + ((port)<<10))
#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)              (0x3600 + ((port)<<10))


#define ETH_UNIT_DFCDL_CONFIGURATION_0                       0x2100    /* NEW */
#define ETH_UNIT_DFCDL_CONFIGURATION_1                       0x2104    /* NEW */
#define ETH_UNIT_DFCDL_STATUS                                0x210C    /* NEW */
#define ETH_UNIT_SRAM_ADDRESS                                0x2110    /* NEW */
#define ETH_UNIT_SRAM_DATA0                                  0x2114    /* NEW */
#define ETH_UNIT_SRAM_DATA1                                  0x2118    /* NEW */
#define ETH_UNIT_DFCDL_PROBE_CTRL                            0x2120    /* NEW */
#define ETH_UNIT_DFCDL_PROBE                                 0x2124    /* NEW */
                                                                      
                                                                      
#define ETH_UNIT_MMASK                                       0x2088    /* NEW */
#define ETH_UNIT_DEBUG0                                      0x208C    /* NEW */
#define ETH_UNIT_DEBUG1                                      0x2090    /* NEW */

    

/*******************************************/
/*          CUNIT  Registers               */
/*******************************************/

         /* Address Decoding Register Map */

#define CUNIT_BASE_ADDR_REG0                                0xf200
#define CUNIT_BASE_ADDR_REG1                                0xf208
#define CUNIT_BASE_ADDR_REG2                                0xf210
#define CUNIT_BASE_ADDR_REG3                                0xf218
#define CUNIT_SIZE0                                         0xf204
#define CUNIT_SIZE1                                         0xf20c
#define CUNIT_SIZE2                                         0xf214
#define CUNIT_SIZE3                                         0xf21c
#define CUNIT_HIGH_ADDR_REMAP_REG0                          0xf240
#define CUNIT_HIGH_ADDR_REMAP_REG1                          0xf244
#define CUNIT_BASE_ADDR_ENABLE_REG                          0xf250
#define MPSC0_ACCESS_PROTECTION_REG                         0xf254
#define MPSC1_ACCESS_PROTECTION_REG                         0xf258
#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG                  0xf25C

        /*  Error Report Registers  */

#define CUNIT_INTERRUPT_CAUSE_REG                           0xf310
#define CUNIT_INTERRUPT_MASK_REG                            0xf314
#define CUNIT_ERROR_ADDR                                    0xf318

        /*  Cunit Control Registers */

#define CUNIT_ARBITER_CONTROL_REG                           0xf300
#define CUNIT_CONFIG_REG                                    0xb40c
#define CUNIT_CRROSBAR_TIMEOUT_REG                          0xf304

        /*  Cunit Debug Registers   */

#define CUNIT_DEBUG_LOW                                     0xf340
#define CUNIT_DEBUG_HIGH                                    0xf344
#define CUNIT_MMASK                                         0xf380

        /*  MPSCs Clocks Routing Registers  */

#define MPSC_ROUTING_REG                                    0xb400
#define MPSC_RX_CLOCK_ROUTING_REG                           0xb404
#define MPSC_TX_CLOCK_ROUTING_REG                           0xb408

        /*  MPSCs Interrupts Registers    */