gt644xx.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

#define PCI_1_COMMAND					    0xc80
#define PCI_0_MODE                                          0xd00
#define PCI_1_MODE                                          0xd80
#define PCI_0_RETRY	        			    0xc04
#define PCI_1_RETRY				            0xc84
#define PCI_0_READ_BUFFER_DISCARD_TIMER                     0xd04
#define PCI_1_READ_BUFFER_DISCARD_TIMER                     0xd84
#define PCI_0_MSI_TRIGGER_TIMER                             0xc38
#define PCI_1_MSI_TRIGGER_TIMER                             0xcb8
#define PCI_0_ARBITER_CONTROL                               0x1d00
#define PCI_1_ARBITER_CONTROL                               0x1d80
#define PCI_0_CROSS_BAR_CONTROL_LOW                         0x1d08
#define PCI_1_CROSS_BAR_CONTROL_LOW                         0x1d88
#define PCI_0_CROSS_BAR_CONTROL_HIGH                        0x1d0c
#define PCI_1_CROSS_BAR_CONTROL_HIGH                        0x1d8c
#define PCI_0_CROSS_BAR_TIMEOUT                             0x1d04
#define PCI_1_CROSS_BAR_TIMEOUT                             0x1d84
#define PCI_0_SYNC_BARRIER_TRIGGER_REG                      0x1D18
#define PCI_1_SYNC_BARRIER_TRIGGER_REG                      0x1D98
#define PCI_0_SYNC_BARRIER_VIRTUAL_REG                      0x1d10
#define PCI_1_SYNC_BARRIER_VIRTUAL_REG                      0x1d90
#define PCI_0_P2P_CONFIG                                    0x1d14
#define PCI_1_P2P_CONFIG                                    0x1d94

#define PCI_0_ACCESS_CONTROL_BASE_0_LOW                     0x1e00
#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH                    0x1e04
#define PCI_0_ACCESS_CONTROL_SIZE_0                         0x1e08
#define PCI_0_ACCESS_CONTROL_BASE_1_LOW                     0x1e10
#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH                    0x1e14
#define PCI_0_ACCESS_CONTROL_SIZE_1                         0x1e18
#define PCI_0_ACCESS_CONTROL_BASE_2_LOW                     0x1e20
#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH                    0x1e24
#define PCI_0_ACCESS_CONTROL_SIZE_2                         0x1e28
#define PCI_0_ACCESS_CONTROL_BASE_3_LOW                     0x1e30
#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH                    0x1e34
#define PCI_0_ACCESS_CONTROL_SIZE_3                         0x1e38
#define PCI_0_ACCESS_CONTROL_BASE_4_LOW                     0x1e40
#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH                    0x1e44
#define PCI_0_ACCESS_CONTROL_SIZE_4                         0x1e48
#define PCI_0_ACCESS_CONTROL_BASE_5_LOW                     0x1e50
#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH                    0x1e54
#define PCI_0_ACCESS_CONTROL_SIZE_5                         0x1e58

#define PCI_1_ACCESS_CONTROL_BASE_0_LOW                     0x1e80
#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH                    0x1e84
#define PCI_1_ACCESS_CONTROL_SIZE_0                         0x1e88
#define PCI_1_ACCESS_CONTROL_BASE_1_LOW                     0x1e90
#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH                    0x1e94
#define PCI_1_ACCESS_CONTROL_SIZE_1                         0x1e98
#define PCI_1_ACCESS_CONTROL_BASE_2_LOW                     0x1ea0
#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH                    0x1ea4
#define PCI_1_ACCESS_CONTROL_SIZE_2                         0x1ea8
#define PCI_1_ACCESS_CONTROL_BASE_3_LOW                     0x1eb0
#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH                    0x1eb4
#define PCI_1_ACCESS_CONTROL_SIZE_3                         0x1eb8
#define PCI_1_ACCESS_CONTROL_BASE_4_LOW                     0x1ec0
#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH                    0x1ec4
#define PCI_1_ACCESS_CONTROL_SIZE_4                         0x1ec8
#define PCI_1_ACCESS_CONTROL_BASE_5_LOW                     0x1ed0
#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH                    0x1ed4
#define PCI_1_ACCESS_CONTROL_SIZE_5                         0x1ed8

/****************************************/
/*   PCI Configuration Access Registers */
/****************************************/

#define PCI_0_CONFIG_ADDR 				    0xcf8
#define PCI_0_CONFIG_DATA_VIRTUAL_REG                       0xcfc
#define PCI_1_CONFIG_ADDR 				    0xc78
#define PCI_1_CONFIG_DATA_VIRTUAL_REG                       0xc7c
#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG	            0xc34
#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG	            0xcb4

/****************************************/
/*   PCI Error Report Registers         */
/****************************************/

#define PCI_0_SERR_MASK					    0xc28
#define PCI_1_SERR_MASK					    0xca8
#define PCI_0_ERROR_ADDR_LOW                                0x1d40
#define PCI_1_ERROR_ADDR_LOW                                0x1dc0
#define PCI_0_ERROR_ADDR_HIGH                               0x1d44
#define PCI_1_ERROR_ADDR_HIGH                               0x1dc4
#define PCI_0_ERROR_ATTRIBUTE                               0x1d48
#define PCI_1_ERROR_ATTRIBUTE                               0x1dc8
#define PCI_0_ERROR_COMMAND                                 0x1d50
#define PCI_1_ERROR_COMMAND                                 0x1dd0
#define PCI_0_ERROR_CAUSE                                   0x1d58
#define PCI_1_ERROR_CAUSE                                   0x1dd8
#define PCI_0_ERROR_MASK                                    0x1d5c
#define PCI_1_ERROR_MASK                                    0x1ddc

/****************************************/
/*   PCI Debug Registers                */
/****************************************/

#define PCI_0_MMASK                                         0X1D24
#define PCI_1_MMASK                                         0X1DA4

/*********************************************/
/* PCI Configuration, Function 0, Registers  */
/*********************************************/

#define PCI_DEVICE_AND_VENDOR_ID 							0x000
#define PCI_STATUS_AND_COMMAND								0x004
#define PCI_CLASS_CODE_AND_REVISION_ID				        0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 		0x00C

#define PCI_SCS_0_BASE_ADDR_LOW   					        0x010
#define PCI_SCS_0_BASE_ADDR_HIGH   					        0x014
#define PCI_SCS_1_BASE_ADDR_LOW  					        0x018
#define PCI_SCS_1_BASE_ADDR_HIGH  					        0x01C
#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW       	0x020
#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH      	0x024
#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID			0x02c
#define PCI_EXPANSION_ROM_BASE_ADDR_REG			            0x030
#define PCI_CAPABILTY_LIST_POINTER                          0x034
#define PCI_INTERRUPT_PIN_AND_LINE 						    0x03C
       /* capability list */
#define PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
#define PCI_VPD_ADDR                                        0x048
#define PCI_VPD_DATA                                        0x04c
#define PCI_MSI_MESSAGE_CONTROL                             0x050
#define PCI_MSI_MESSAGE_ADDR                                0x054
#define PCI_MSI_MESSAGE_UPPER_ADDR                          0x058
#define PCI_MSI_MESSAGE_DATA                                0x05c
#define PCI_X_COMMAND                                       0x060
#define PCI_X_STATUS                                        0x064
#define PCI_COMPACT_PCI_HOT_SWAP                            0x068

/***********************************************/
/*   PCI Configuration, Function 1, Registers  */
/***********************************************/

#define PCI_SCS_2_BASE_ADDR_LOW   						    0x110
#define PCI_SCS_2_BASE_ADDR_HIGH						    0x114
#define PCI_SCS_3_BASE_ADDR_LOW 							0x118
#define PCI_SCS_3_BASE_ADDR_HIGH					        0x11c
#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW          	        0x120
#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH         	        0x124

/***********************************************/
/*  PCI Configuration, Function 2, Registers   */
/***********************************************/

#define PCI_DEVCS_0_BASE_ADDR_LOW	    			        0x210
#define PCI_DEVCS_0_BASE_ADDR_HIGH 					        0x214
#define PCI_DEVCS_1_BASE_ADDR_LOW 					        0x218
#define PCI_DEVCS_1_BASE_ADDR_HIGH      			        0x21c
#define PCI_DEVCS_2_BASE_ADDR_LOW 					        0x220
#define PCI_DEVCS_2_BASE_ADDR_HIGH      			        0x224

/***********************************************/
/*  PCI Configuration, Function 3, Registers   */
/***********************************************/

#define PCI_DEVCS_3_BASE_ADDR_LOW	    			        0x310
#define PCI_DEVCS_3_BASE_ADDR_HIGH 					        0x314
#define PCI_BOOT_CS_BASE_ADDR_LOW					        0x318
#define PCI_BOOT_CS_BASE_ADDR_HIGH      			        0x31c
#define PCI_CPU_BASE_ADDR_LOW 						        0x320
#define PCI_CPU_BASE_ADDR_HIGH      			            0x324

/***********************************************/
/*  PCI Configuration, Function 4, Registers   */
/***********************************************/

#define PCI_P2P_MEM0_BASE_ADDR_LOW  					    0x410
#define PCI_P2P_MEM0_BASE_ADDR_HIGH 				        0x414
#define PCI_P2P_MEM1_BASE_ADDR_LOW   				        0x418
#define PCI_P2P_MEM1_BASE_ADDR_HIGH 				        0x41c
#define PCI_P2P_I_O_BASE_ADDR                 	            0x420
#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR              0x424

/****************************************/
/* Messaging Unit Registers (I20)   	*/
/****************************************/

#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE			        0x010
#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE  		        0x014
#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 		        0x018
#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE  		        0x01C
#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE  		        0x020
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE          0x024
#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	        0x028
#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 		        0x02C
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE         0x030
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE          0x034
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE       0x040
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE      0x044
#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 				    0x050
#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 			        0x054
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE        0x060
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE        0x064
#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE        0x068
#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE        0x06C
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE       0x070
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE       0x074
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE       0x078
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE       0x07C

#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE			        0x090
#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE  		        0x094
#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 		        0x098
#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE  		        0x09C
#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE  		        0x0A0
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE          0x0A4
#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	        0x0A8
#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 		        0x0AC
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE         0x0B0
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE          0x0B4
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE       0x0C0
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE      0x0C4
#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 				    0x0D0
#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 			        0x0D4
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE        0x0E0
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE        0x0E4
#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE        0x0E8
#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE        0x0EC
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE       0x0F0
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE       0x0F4
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE       0x0F8
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE       0x0FC

#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE			        0x1C10
#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE  		        0x1C14
#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 		        0x1C18
#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE  		        0x1C1C
#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE  		        0x1C20
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE  	        0x1C24
#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	        0x1C28
#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 		        0x1C2C
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE          0x1C30
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE           0x1C34
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE        0x1C40
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE       0x1C44
#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE 			        0x1C50
#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 		            0x1C54
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE        	0x1C60
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE         0x1C64
#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE         0x1C68