gt644xx.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

#define CPU_ERROR_PARITY                                    0x138
#define CPU_ERROR_CAUSE                                     0x140
#define CPU_ERROR_MASK                                      0x148

/****************************************/
/*      CPU Interface Debug Registers 	*/
/****************************************/

#define PUNIT_SLAVE_DEBUG_LOW                               0x360
#define PUNIT_SLAVE_DEBUG_HIGH                              0x368
#define PUNIT_MASTER_DEBUG_LOW                              0x370
#define PUNIT_MASTER_DEBUG_HIGH                             0x378
#define PUNIT_MMASK                                         0x3e4
#define PUNIT_TCAM_UNMAPPED_0                               0x1d0      /* NEW */
#define PUNIT_TCAM_UNMAPPED_1                               0x1c8      /* NEW */
#define PUNIT_TCAM_UNMAPPED_2                               0x1e0      /* NEW */
#define PUNIT_TCAM_UNMAPPED_3                               0x1d8      /* NEW */
#define PUNIT_TCAM_UNMAPPED_4                               0x1f0      /* NEW */
#define PUNIT_TCAM_UNMAPPED_5                               0x1e8      /* NEW */
#define PUNIT_TCAM_UNMAPPED_6                               0x1f8      /* NEW */
#define PUNIT_TCAM_UNMAPPED_7                               0x178      /* NEW */




/****************************************/
/*  Integrated SRAM Registers           */
/****************************************/

#define SRAM_CONFIG_REG                                     0x380
       /* tissa- Added for 64360 backward compatibility */
#define SRAM_CONFIG            SRAM_CONFIG_REG
#define SRAM_TEST_MODE                                      0X3F4
#define SRAM_ERROR_CAUSE                                    0x388
#define SRAM_ERROR_MASK                                     0x2d8      /* NEW */
#define SRAM_ERROR_ADDR                                     0x390
#define SRAM_ERROR_ADDR_HIGH                                0X3F8
#define SRAM_ERROR_DATA_LOW                                 0x398
#define SRAM_ERROR_DATA_HIGH                                0x3a0
#define SRAM_ERROR_DATA_PARITY                              0x3a8
#define SRAM_ECC_SINGLE_BIT_ERROR_CNTR                      0x2e0      /* NEW */
#define SRAM_ECC_DOUBLE_BIT_ERROR_CNTR                      0x2e8      /* NEW */


/****************************************/
/* SDRAM Configuration                  */
/****************************************/

#define SDRAM_CONFIG_REG                                    0x1400
       /* tissa- Added for 64360 backward compatibility */
#define SDRAM_CONFIG           SDRAM_CONFIG_REG

#define D_UNIT_CONTROL_LOW                                  0x1404
#define D_UNIT_CONTROL_HIGH                                 0x1424
#define SDRAM_TIMING_CONTROL_LOW                            0x1408
#define SDRAM_TIMING_CONTROL_HIGH                           0x140c
#define FCRAM_TIMING                                        0x1428     /* NEW */
#define SDRAM_ADDR_CONTROL                                  0x1410
#define SDRAM_OPEN_PAGES_CONTROL                            0x1414
#define SDRAM_OPERATION                                     0x1418
#define SDRAM_MODE                                          0x141c
#define EXTENDED_DRAM_MODE                                  0x1420
#define SDRAM_CROSS_BAR_CONTROL_LOW                         0x1430
#define SDRAM_CROSS_BAR_CONTROL_HIGH                        0x1434
#define SDRAM_CROSS_BAR_TIMEOUT                             0x1438
#define SDRAM_ADDR_CTRL_PADS_CALIBRATION                    0x14c0
#define SDRAM_DATA_PADS_CALIBRATION                         0x14c4

/****************************************/
/* SDRAM Error Report                   */
/****************************************/

#define SDRAM_DUNIT_INTERRUPT_CAUSE                         0x14d0     /* NEW */
#define SDRAM_DUNIT_INTERRUPT_MASK                          0x14d4     /* NEW */
#define SDRAM_ERROR_DATA_LOW                                0x1444
#define SDRAM_ERROR_DATA_HIGH                               0x1440
#define SDRAM_ERROR_ADDR                                    0x1450
#define SDRAM_RECEIVED_ECC                                  0x1448
#define SDRAM_CALCULATED_ECC                                0x144c
#define SDRAM_ECC_CONTROL                                   0x1454
#define SDRAM_CS0_SINGLE_BIT_ERROR_CNTR                     0x1458     /* NEW */   
#define SDRAM_CS0_DOUBLE_BIT_ERROR_CNTR                     0x145c     /* NEW */   
#define SDRAM_CS1_SINGLE_BIT_ERROR_CNTR                     0x1460     /* NEW */   
#define SDRAM_CS1_DOUBLE_BIT_ERROR_CNTR                     0x1464     /* NEW */   
#define SDRAM_CS2_SINGLE_BIT_ERROR_CNTR                     0x1468     /* NEW */   
#define SDRAM_CS2_DOUBLE_BIT_ERROR_CNTR                     0x146c     /* NEW */   
#define SDRAM_CS3_SINGLE_BIT_ERROR_CNTR                     0x1470     /* NEW */   
#define SDRAM_CS3_DOUBLE_BIT_ERROR_CNTR                     0x1474     /* NEW */   

/******************************************/
/*  Controlled Delay Line (CDL) Registers */
/******************************************/

#define DFCDL_CONFIG0                                       0x1480
#define DFCDL_CONFIG1                                       0x1484
#define DLL_WRITE                                           0x1488
#define DLL_READ                                            0x148c
#define SRAM_ADDR                                           0x1490
#define SRAM_DATA0                                          0x1494
#define SRAM_DATA1                                          0x1498
#define SRAM_DATA2                                          0x149c
#define DFCL_PROBE                                          0x14a0
#define DFCDL_DEBUG                                         0x14a4     /* NEW */

/******************************************/
/*   Debug Registers                      */
/******************************************/

#define DUNIT_DEBUG_LOW                                     0x14b4 /* CHANGED */
#define DUNIT_DEBUG_HIGH                                    0x14b8 /* CHANGED */
#define DUNIT_MMASK                                         0X14b0 /* CHANGED */

/****************************************/
/* Device Parameters					*/
/****************************************/

#define DEVICE_BANK0_PARAMETERS								0x45c
#define DEVICE_BANK1_PARAMETERS								0x460
#define DEVICE_BANK2_PARAMETERS								0x464
#define DEVICE_BANK3_PARAMETERS								0x468
#define DEVICE_BOOT_BANK_PARAMETERS							0x46c
#define DEVICE_INTERFACE_CONTROL                            0x4c0
#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW              0x4c8
#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH             0x4cc
#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT                  0x4c4

/****************************************/
/* Device interrupt registers			*/
/****************************************/

#define DEVICE_INTERRUPT_CAUSE								0x4d0
#define DEVICE_INTERRUPT_MASK								0x4d4
#define DEVICE_ERROR_ADDR								    0x4d8
#define DEVICE_ERROR_DATA   								0x4dc
#define DEVICE_ERROR_PARITY     							0x4e0

/****************************************/
/* Device debug registers   			*/
/****************************************/

#define DEVICE_DEBUG_LOW     						        0x4e8 /* Offset Changed */
#define DEVICE_DEBUG_HIGH     						        0x4ec /* Offset Changed */
#define RUNIT_MMASK                                         0x4f0

/****************************************/
/* PCI Slave Address Decoding registers */
/****************************************/

#define PCI_0_CS_0_BANK_SIZE                                0xc08
#define PCI_1_CS_0_BANK_SIZE                                0xc88
#define PCI_0_CS_1_BANK_SIZE                                0xd08
#define PCI_1_CS_1_BANK_SIZE                                0xd88
#define PCI_0_CS_2_BANK_SIZE                                0xc0c
#define PCI_1_CS_2_BANK_SIZE                                0xc8c
#define PCI_0_CS_3_BANK_SIZE                                0xd0c
#define PCI_1_CS_3_BANK_SIZE                                0xd8c
#define PCI_0_DEVCS_0_BANK_SIZE                             0xc10
#define PCI_1_DEVCS_0_BANK_SIZE                             0xc90
#define PCI_0_DEVCS_1_BANK_SIZE                             0xd10
#define PCI_1_DEVCS_1_BANK_SIZE                             0xd90
#define PCI_0_DEVCS_2_BANK_SIZE                             0xd18
#define PCI_1_DEVCS_2_BANK_SIZE                             0xd98
#define PCI_0_DEVCS_3_BANK_SIZE                             0xc14
#define PCI_1_DEVCS_3_BANK_SIZE                             0xc94
#define PCI_0_DEVCS_BOOT_BANK_SIZE                          0xd14
#define PCI_1_DEVCS_BOOT_BANK_SIZE                          0xd94
#define PCI_0_P2P_MEM0_BAR_SIZE                             0xd1c
#define PCI_1_P2P_MEM0_BAR_SIZE                             0xd9c
#define PCI_0_P2P_MEM1_BAR_SIZE                             0xd20
#define PCI_1_P2P_MEM1_BAR_SIZE                             0xda0
#define PCI_0_P2P_I_O_BAR_SIZE                              0xd24
#define PCI_1_P2P_I_O_BAR_SIZE                              0xda4
#define PCI_0_CPU_BAR_SIZE                                  0xd28
#define PCI_1_CPU_BAR_SIZE                                  0xda8
#define PCI_0_INTERNAL_SRAM_BAR_SIZE                        0xe00
#define PCI_1_INTERNAL_SRAM_BAR_SIZE                        0xe80
#define PCI_0_EXPANSION_ROM_BAR_SIZE                        0xd2c
#define PCI_1_EXPANSION_ROM_BAR_SIZE                        0xd9c
#define PCI_0_BASE_ADDR_REG_ENABLE                          0xc3c
#define PCI_1_BASE_ADDR_REG_ENABLE                          0xcbc
#define PCI_0_CS_0_BASE_ADDR_REMAP					        0xc48
#define PCI_1_CS_0_BASE_ADDR_REMAP					        0xcc8
#define PCI_0_CS_1_BASE_ADDR_REMAP					        0xd48
#define PCI_1_CS_1_BASE_ADDR_REMAP					        0xdc8
#define PCI_0_CS_2_BASE_ADDR_REMAP					        0xc4c
#define PCI_1_CS_2_BASE_ADDR_REMAP					        0xccc
#define PCI_0_CS_3_BASE_ADDR_REMAP					        0xd4c
#define PCI_1_CS_3_BASE_ADDR_REMAP					        0xdcc
#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP				        0xF04
#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP				        0xF84
#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP				        0xF08
#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP				        0xF88
#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP				        0xF0C
#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP				        0xF8C
#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP				        0xF10
#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP				        0xF90
#define PCI_0_DEVCS_0_BASE_ADDR_REMAP				        0xc50
#define PCI_1_DEVCS_0_BASE_ADDR_REMAP				        0xcd0
#define PCI_0_DEVCS_1_BASE_ADDR_REMAP				        0xd50
#define PCI_1_DEVCS_1_BASE_ADDR_REMAP				        0xdd0
#define PCI_0_DEVCS_2_BASE_ADDR_REMAP				        0xd58
#define PCI_1_DEVCS_2_BASE_ADDR_REMAP				        0xdd8
#define PCI_0_DEVCS_3_BASE_ADDR_REMAP           			0xc54
#define PCI_1_DEVCS_3_BASE_ADDR_REMAP           			0xcd4
#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP      			0xd54
#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP      			0xdd4
#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW                  0xd5c
#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW                  0xddc
#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH                 0xd60
#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH                 0xde0
#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW                  0xd64
#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW                  0xde4
#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH                 0xd68
#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH                 0xde8
#define PCI_0_P2P_I_O_BASE_ADDR_REMAP                       0xd6c
#define PCI_1_P2P_I_O_BASE_ADDR_REMAP                       0xdec
#define PCI_0_CPU_BASE_ADDR_REMAP_LOW                       0xd70
#define PCI_1_CPU_BASE_ADDR_REMAP_LOW                       0xdf0
#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH                      0xd74
#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH                      0xdf4
#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP               0xf00
#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP               0xf80
#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP                 0xf38
#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP                 0xfb8
#define PCI_0_ADDR_DECODE_CONTROL                           0xd3c
#define PCI_1_ADDR_DECODE_CONTROL                           0xdbc
#define PCI_0_HEADERS_RETARGET_CONTROL                      0xF40
#define PCI_1_HEADERS_RETARGET_CONTROL                      0xFc0
#define PCI_0_HEADERS_RETARGET_BASE                         0xF44
#define PCI_1_HEADERS_RETARGET_BASE                         0xFc4
#define PCI_0_HEADERS_RETARGET_HIGH                         0xF48
#define PCI_1_HEADERS_RETARGET_HIGH                         0xFc8

/***********************************/
/*   PCI Control Register Map      */
/***********************************/

#define PCI_0_DLL_STATUS_AND_COMMAND                        0x1d20
#define PCI_1_DLL_STATUS_AND_COMMAND                        0x1da0
#define PCI_0_MPP_PADS_DRIVE_CONTROL                        0x1d1C
#define PCI_1_MPP_PADS_DRIVE_CONTROL                        0x1d9C
#define PCI_0_COMMAND					    0xc00