gt644xx.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* gt6446xx.h - Header File for GT-644xx registers */
/**************************************************************************
 *
 *   Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights
 *   reserved.  This Source Code is the Property of Curtiss-Wright
 *   Controls, Inc. and can only be used in accordance with Source
 *   Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any
 *   of its subsidiaries.
 *
 **************************************************************************/
/*******************************************************************************
*         Copyright 2003, 1.3.1 SEMICONDUCTOR ISRAEL, LTD.                   *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*                                                                              *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), MARVELL SEMICONDUCTOR ISRAEL. (MSIL),  MARVELL TAIWAN, LTD. AND      *
* SYSKONNECT GMBH.                                                             *
********************************************************************************


modification history
--------------------
01c,13oct05,tis     added PCI ERRORS to support CR#12215.
01b,30nov04,tis     fixed the macro BRG_BAUDE_TUNING_REG
01a,19nov04,tis     derrive from MARVELL BSP DB-644xx Ver 1.3.1
*/
#ifndef __INCgt64460rh
#define __INCgt64460rh

#ifdef __cplusplus
extern "C" {
#endif

#define DISCO_NAME   "MV-64460"

/* Supported by the Aristo */
#define INCLUDE_PCI_1
#define INCLUDE_PCI_0_ARBITER
#define INCLUDE_PCI_1_ARBITER
#define INCLUDE_SNOOP_SUPPORT
#define INCLUDE_P2P
#define INCLUDE_ETH_PORT_2
#define INCLUDE_CPU_MAPPING
#define INCLUDE_MPSC
#define INCLUDE_INTERNAL_SRAM

#if defined (MV6446x)

#   define INCLUDE_HW_CACHE_COHERENCY

/* Bits in CPU Mode register (0x120) */
/* CPU_Type: bits[4..7]      */
#   define CPU_TYPE_OFFSET          4
#   define CPU_TYPE_MASK            (0xF << CPU_TYPE_OFFSET) 
#   define CPU_TYPE_PPC64_60x       (4 << CPU_TYPE_OFFSET)
#   define CPU_TYPE_PPC64_MPX       (5 << CPU_TYPE_OFFSET)

/* Bits in CPU Master register (0x160) */
#   define CPU_INT_ARBITER_BIT      8
#   define CPU_INT_ARBITER_MASK     (1 << CPU_INT_ARBITER_BIT)

#   define CPU_CLEAN_BLOCK_BIT      12
#   define CPU_CLEAN_BLOCK_MASK     (1 << CPU_CLEAN_BLOCK_BIT)

#   define CPU_CLEAN_FLUSH_BIT      13
#   define CPU_CLEAN_FLUSH_MASK     (1 << CPU_CLEAN_FLUSH_BIT)

#endif /* (MV6446x) */

/* Not supported features */
#undef  INCLUDE_CNTMR_4_7
#undef  INCLUDE_DMA_4_7

/****************************************/
/* Processor Address Space              */
/****************************************/

/* DDR SDRAM BAR and size registers */

#define CS_0_BASE_ADDR                                      0x008
#define CS_0_SIZE                                           0x010
#define CS_1_BASE_ADDR                                      0x208
#define CS_1_SIZE                                           0x210
#define CS_2_BASE_ADDR                                      0x018
#define CS_2_SIZE                                           0x020
#define CS_3_BASE_ADDR                                      0x218
#define CS_3_SIZE                                           0x220

/* Devices BAR and size registers */

#define DEV_CS0_BASE_ADDR                                   0x028
#define DEV_CS0_SIZE                                        0x030
#define DEV_CS1_BASE_ADDR                                   0x228
#define DEV_CS1_SIZE                                        0x230
#define DEV_CS2_BASE_ADDR                                   0x248
#define DEV_CS2_SIZE                                        0x250
#define DEV_CS3_BASE_ADDR                                   0x038
#define DEV_CS3_SIZE                                        0x040
#define BOOTCS_BASE_ADDR                                    0x238
#define BOOTCS_SIZE                                         0x240

/* PCI 0 BAR and size registers */

#define PCI_0_IO_BASE_ADDR                                  0x048
#define PCI_0_IO_SIZE                                       0x050
#define PCI_0_MEMORY0_BASE_ADDR                             0x058
#define PCI_0_MEMORY0_SIZE                                  0x060
#define PCI_0_MEMORY1_BASE_ADDR                             0x080
#define PCI_0_MEMORY1_SIZE                                  0x088
#define PCI_0_MEMORY2_BASE_ADDR                             0x258
#define PCI_0_MEMORY2_SIZE                                  0x260
#define PCI_0_MEMORY3_BASE_ADDR                             0x280
#define PCI_0_MEMORY3_SIZE                                  0x288

/* PCI 1 BAR and size registers */
#define PCI_1_IO_BASE_ADDR                                  0x090
#define PCI_1_IO_SIZE                                       0x098
#define PCI_1_MEMORY0_BASE_ADDR                             0x0a0
#define PCI_1_MEMORY0_SIZE                                  0x0a8
#define PCI_1_MEMORY1_BASE_ADDR                             0x0b0
#define PCI_1_MEMORY1_SIZE                                  0x0b8
#define PCI_1_MEMORY2_BASE_ADDR                             0x2a0
#define PCI_1_MEMORY2_SIZE                                  0x2a8
#define PCI_1_MEMORY3_BASE_ADDR                             0x2b0
#define PCI_1_MEMORY3_SIZE                                  0x2b8

/* SRAM base address */
#define INTEGRATED_SRAM_BASE_ADDR                           0x268

/* internal registers space base address */
#define INTERNAL_SPACE_BASE_ADDR                            0x068

/* Enables the CS , DEV_CS , PCI 0 and PCI 1
   windows above */
#define BASE_ADDR_ENABLE                                    0x278

/****************************************/
/* PCI remap registers                  */
/****************************************/
      /* PCI 0 */
#define PCI_0_IO_ADDR_REMAP                                 0x0f0
#define PCI_0_MEMORY0_LOW_ADDR_REMAP                        0x0f8
#define PCI_0_MEMORY0_HIGH_ADDR_REMAP                       0x320
#define PCI_0_MEMORY1_LOW_ADDR_REMAP                        0x100
#define PCI_0_MEMORY1_HIGH_ADDR_REMAP                       0x328
#define PCI_0_MEMORY2_LOW_ADDR_REMAP                        0x2f8
#define PCI_0_MEMORY2_HIGH_ADDR_REMAP                       0x330
#define PCI_0_MEMORY3_LOW_ADDR_REMAP                        0x300
#define PCI_0_MEMORY3_HIGH_ADDR_REMAP                       0x338
      /* PCI 1 */
#define PCI_1_IO_ADDR_REMAP                                 0x108
#define PCI_1_MEMORY0_LOW_ADDR_REMAP                        0x110
#define PCI_1_MEMORY0_HIGH_ADDR_REMAP                       0x340
#define PCI_1_MEMORY1_LOW_ADDR_REMAP                        0x118
#define PCI_1_MEMORY1_HIGH_ADDR_REMAP                       0x348
#define PCI_1_MEMORY2_LOW_ADDR_REMAP                        0x310
#define PCI_1_MEMORY2_HIGH_ADDR_REMAP                       0x350
#define PCI_1_MEMORY3_LOW_ADDR_REMAP                        0x318
#define PCI_1_MEMORY3_HIGH_ADDR_REMAP                       0x358

#define CPU_PCI_0_HEADERS_RETARGET_CONTROL                  0x3b0
#define CPU_PCI_0_HEADERS_RETARGET_BASE                     0x3b8
#define CPU_PCI_1_HEADERS_RETARGET_CONTROL                  0x3c0
#define CPU_PCI_1_HEADERS_RETARGET_BASE                     0x3c8
#define CPU_GE_HEADERS_RETARGET_CONTROL                     0x3d0
#define CPU_GE_HEADERS_RETARGET_BASE                        0x3d8
#define CPU_IDMA_HEADERS_RETARGET_CONTROL                   0x3e0
#define CPU_IDMA_HEADERS_RETARGET_BASE                      0x3e8

/****************************************/
/*         CPU Control Registers        */
/****************************************/

#define CPU_CONFIG                                          0x000
#define CPU_MODE                                            0x120
#define CPU_MASTER_CONTROL                                  0x160
#define CPU_CROSS_BAR_CONTROL_LOW                           0x150
#define CPU_CROSS_BAR_CONTROL_HIGH                          0x158
#define CPU_CROSS_BAR_TIMEOUT                               0x168
#define CPU_SYNC_BARRIER_CONTROL                            0x1C0      /* NEW */
#define CPU_ORDERING_DEADLOCK_CONTROL                       0x2d0      /* NEW */
#define CPU_PADS_CALIBRATION                                0x3b4
#define CPU_SLAVE_CONTROL                                   0x3F0      /* NEW */

/****************************************/
/* SMP RegisterS                        */
/****************************************/

#define SMP_WHO_AM_I                                        0x200
#define SMP_CPU0_DOORBELL                                   0x214
#define SMP_CPU0_DOORBELL_CLEAR                             0x21C
#define SMP_CPU1_DOORBELL                                   0x224
#define SMP_CPU1_DOORBELL_CLEAR                             0x22C
#define SMP_CPU0_DOORBELL_MASK                              0x234
#define SMP_CPU1_DOORBELL_MASK                              0x23C
#define SMP_SEMAPHOR0                                       0x244
#define SMP_SEMAPHOR1                                       0x24c
#define SMP_SEMAPHOR2                                       0x254
#define SMP_SEMAPHOR3                                       0x25c
#define SMP_SEMAPHOR4                                       0x264
#define SMP_SEMAPHOR5                                       0x26c
#define SMP_SEMAPHOR6                                       0x274
#define SMP_SEMAPHOR7                                       0x27c

/****************************************/
/*  CPU Sync Barrier Register           */
/****************************************/

#define CPU_0_SYNC_BARRIER_TRIGGER                          0x0c0
#define CPU_0_SYNC_BARRIER_VIRTUAL                          0x0c8
#define CPU_1_SYNC_BARRIER_TRIGGER                          0x0d0
#define CPU_1_SYNC_BARRIER_VIRTUAL                          0x0d8

/****************************************/
/* CPU Access Protect                   */
/****************************************/

#define CPU_PROTECT_WINDOW_0_BASE_ADDR                      0x180
#define CPU_PROTECT_WINDOW_0_SIZE                           0x188
#define CPU_PROTECT_WINDOW_1_BASE_ADDR                      0x190
#define CPU_PROTECT_WINDOW_1_SIZE                           0x198
#define CPU_PROTECT_WINDOW_2_BASE_ADDR                      0x1a0
#define CPU_PROTECT_WINDOW_2_SIZE                           0x1a8
#define CPU_PROTECT_WINDOW_3_BASE_ADDR                      0x1b0
#define CPU_PROTECT_WINDOW_3_SIZE                           0x1b8


/****************************************/
/*          CPU Error Report            */
/****************************************/

#define CPU_ERROR_ADDR_LOW                                  0x070
#define CPU_ERROR_ADDR_HIGH                                 0x078
#define CPU_ERROR_DATA_LOW                                  0x128
#define CPU_ERROR_DATA_HIGH                                 0x130