gtcore_dy4.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* Read/Write to/from GT`s internal registers */
#ifndef GT_REG_READ
    #define GT_REG_READ(a, b) (*(b) = _readSwap( (char *) ((a) + CPU_DISCO2_BASE_ADRS) ) )
#endif /* GT_REG_READ */

#ifndef GT_REG_WRITE

 #define GT_REG_WRITE(a, b)	_writeSwap( (char *) ( (a) + CPU_DISCO2_BASE_ADRS ), (b))

#endif /* GT_REG_WRITE */

/* Write 32/16/8 bit NonCacheable */

#define GT_WRITE_CHAR(address, data)                                           \
        ((*((volatile unsigned char *)NONE_CACHEABLE((address))))=             \
        ((unsigned char)(data)))

#define GT_WRITE_SHORT(address, data)                                          \
        ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) =           \
        ((unsigned short)(data)))

#define GT_WRITE_WORD(a, b)		_writeSwap((void *)(a), (b))

/* Write 32/16/8 bit Cacheable */
#define GT_WRITE_CHAR_CACHEABLE(address, data)                                 \
        ((*((volatile unsigned char *)CACHEABLE(address))) =                   \
        ((unsigned char)(data)))

#define GT_WRITE_SHORT_CACHEABLE(address, data)                                \
        ((*((volatile unsigned short *)CACHEABLE(address))) =                  \
        ((unsigned short)(data)))

#define GT_WRITE_WORD_CACHEABLE(address, data)                                 \
        ((*((volatile unsigned int *)CACHEABLE(address))) =                    \
        ((unsigned int)(data)))

/* Read 32/16/8 bits NonCacheable - returns data in variable. */
#define GT_READ_CHAR(address, pData)                                           \
        (*(pData) = (*((volatile unsigned char *)NONE_CACHEABLE(address))))

#define GT_READ_SHORT(address, pData)                                          \
        (*(pData) = (*((volatile unsigned short *)NONE_CACHEABLE(address))))

#define GT_READ_WORD(address, pData) GT_REG_READ(adress, pData)

/* Read 32/16/8 bit NonCacheable - returns data direct. */
#define GT_READCHAR(address)                                                   \
        ((*((volatile unsigned char *)NONE_CACHEABLE(address))))

#define GT_READSHORT(address)                                                  \
        ((*((volatile unsigned short *)NONE_CACHEABLE(address))))

#define GT_READWORD(address)                                                   \
        ((*((volatile unsigned int *)NONE_CACHEABLE(address))))

/* Read 32/16/8 bit Cacheable */
#define GT_READ_CHAR_CACHEABLE(address, pData)                                 \
        (*(pData) = (*((unsigned char *)CACHEABLE(address))))

#define GT_READ_SHORT_CACHEABLE(address, pData)                                \
        (*(pData) = (*((unsigned short *)CACHEABLE(address))))

#define GT_READ_WORD_CACHEABLE(address, pData)                                 \
        (*(pData) = (*((unsigned int *)CACHEABLE(address))))

/* Read 32/16/8 bit Cacheable - returns data direct. */
#define GT_READCHAR_CACHEABLE(address)                                         \
        ((*((unsigned char *)CACHEABLE(address))))

#define GT_READSHORT_CACHEABLE(address)                                        \
        ((*((unsigned short *)CACHEABLE(address))))

#define GT_READWORD_CACHEABLE(address)                                         \
        ((*((unsigned int *)CACHEABLE(address))))

/* gets register offset and bits: a 32bit value. It set to logic '1' in the
   internal register the bits which given as an input example:
   GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
   '1' in register 0x840 while the other bits stays as is. */
#define GT_SET_REG_BITS(regOffset,bits)                                        \
        ((*((volatile unsigned int*)(NONE_CACHEABLE(gtInternalRegBaseAddr) |   \
        (regOffset)))) |= ((unsigned int)GT_WORD_SWAP(bits)))

/* gets register offset and bits: a 32bit value. It set to logic '0' in the
   internal register the bits which given as an input example:
   GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
   logic '0' in register 0x840 while the other bits stays as is. */
#define GT_RESET_REG_BITS(regOffset,bits)                                      \
        ((*((volatile unsigned int*)(NONE_CACHEABLE(gtInternalRegBaseAddr) |   \
        (regOffset)))) &= ~((unsigned int)GT_WORD_SWAP(bits)))

#define REG_ADDR(offset)      (NONE_CACHEABLE(gtInternalRegBaseAddr | (offset)))
#define REG_CONTENT(offset)   ((volatile unsigned int)                         \
                                               *(unsigned int*)REG_ADDR(offset))
                                               
#define GT_REG_CHAR_READ(a, b)      GT_READ_CHAR(a + CPU_DISCO2_BASE_ADRS, b)

#define GT_REG_CHAR_WRITE(a, b)     GT_WRITE_CHAR(a + CPU_DISCO2_BASE_ADRS, b)                                               
/*
 * Address Decode Parameters
 */
     
/* Base Address Register bits */
#define BAR_TARGET_DRAM                    0x00000000
#define BAR_TARGET_DEVICE                  0x00000001
#define BAR_TARGET_CBS                     0x00000002
#define BAR_TARGET_PCI0                    0x00000003
#define BAR_TARGET_PCI1                    0x00000004
#define BAR_TARGET_CUNIT                   0x00000005
#define BAR_TARGET_AUNIT                   0x00000006
#define BAR_TARGET_GUNIT                   0x00000007

/* Window attributes */
#define BAR_ATTR_DRAM_CS0		0x00000E00
#define BAR_ATTR_DRAM_CS1		0x00000D00
#define BAR_ATTR_DRAM_CS2		0x00000B00
#define BAR_ATTR_DRAM_CS3		0x00000700

/* CPU 60x bus or internal SRAM interface */
#define BAR_ATTR_CBS_SRAM_BLOCK0           0x00000000
#define BAR_ATTR_CBS_SRAM_BLOCK1           0x00000100
#define BAR_ATTR_CBS_SRAM                  0x00000000
#define BAR_ATTR_CBS_CPU_BUS               0x00000800

   /* Device Bus Target interface */
#define BAR_ATTR_DEVICE_DEVCS0             0x00001E00
#define BAR_ATTR_DEVICE_DEVCS1             0x00001D00
#define BAR_ATTR_DEVICE_DEVCS2             0x00001B00
#define BAR_ATTR_DEVICE_DEVCS3             0x00001700
#define BAR_ATTR_DEVICE_BOOTCS3            0x00000F00
     
 /* DRAM Target interface */
#define BAR_ATTR_DRAM_NO_CACHE_COHERENCY      0x00000000
#define BAR_ATTR_DRAM_CACHE_COHERENCY_WT      0x00001000
#define BAR_ATTR_DRAM_CACHE_COHERENCY_WB      0x00002000
 
 /* Device Bus Target interface */
#define BAR_ATTR_DEVICE_DEVCS0                                0x00001E00
#define BAR_ATTR_DEVICE_DEVCS1                                0x00001D00
#define BAR_ATTR_DEVICE_DEVCS2                                0x00001B00
#define BAR_ATTR_DEVICE_DEVCS3                                0x00001700
#define BAR_ATTR_DEVICE_BOOTCS3                           0x00000F00
 
 /* PCI Target interface */
#define BAR_ATTR_PCI_BYTE_SWAP                                0x00000000
#define BAR_ATTR_PCI_NO_SWAP                          0x00000100
#define BAR_ATTR_PCI_BYTE_WORD_SWAP               0x00000200
#define BAR_ATTR_PCI_WORD_SWAP                                0x00000300
#define BAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT      0x00000000
#define BAR_ATTR_PCI_NO_SNOOP_ASSERT          0x00000400
#define BAR_ATTR_PCI_IO_SPACE                         0x00000000
#define BAR_ATTR_PCI_MEMORY_SPACE                     0x00000800
#define BAR_ATTR_PCI_REQ64_FORCE                      0x00000000
#define BAR_ATTR_PCI_REQ64_SIZE                           0x00001000
      
/*
 * Window access control
 */
#define WIN_ACCESS_NOT_ALLOWED              0
#define WIN_ACCESS_READ_ONLY                BIT0
#define WIN_ACCESS_FULL                     (BIT1 | BIT0)

typedef enum _addrWin 
{
	ADDR_WIN0, 
	ADDR_WIN1, 
	ADDR_WIN2, 
	ADDR_WIN3, 
	ADDR_WIN4, 
	ADDR_WIN5, 
	ADDR_WIN6, 
	ADDR_WIN7 
} ADDR_WIN;

typedef enum _addrWinTarget
{
	TARGET_DRAM  ,
	TARGET_DEVICE,
	TARGET_CBS   ,
	TARGET_PCI0  ,
	TARGET_PCI1  
} ADDR_WIN_TARGET;

typedef struct _addrWinParam
{
    ADDR_WIN 	    win;		/* Window number. See CUNIT_ADDR_WIN enum   */
    ADDR_WIN_TARGET target;     /* System targets. See CUNIT_TARGET enum	*/
    unsigned short 	attributes;	/* BAR attributes. See above macros.		*/
    unsigned int 	baseAddr;	/* Window base address in unsigned int form */
    unsigned int 	highAddr;   /* Window high address in unsigned int form */
    unsigned int 	size; 		/* Size in MBytes. Must be % 64Kbyte. 		*/
    int 			enable;     /* Enable/disable access to the window.     */
    unsigned short 	accessCtrl; /* Access ctrl register. see above macros 	*/
} ADDR_WIN_PARAM;
    

#ifdef __cplusplus
}
#endif

#endif /* __INCgtCoreh */