📄 gtcore_dy4.h
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/* gtCore_dy4.h - Header File for basic GT core logic functions and definitions *//************************************************************************** * * Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights * reserved. This Source Code is the Property of Curtiss-Wright * Controls, Inc. and can only be used in accordance with Source * Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any * of its subsidiaries. * **************************************************************************//******************************************************************************** Copyright 2002, GALILEO TECHNOLOGY, LTD. ** THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. ** NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT ** OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE ** DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. ** THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, ** IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. ** ** MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, ** MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL ** SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. ** (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI). *********************************************************************************//*modification history--------------------01i,06dec05,tis add support for SCP-12401h,26sep05,asu add support for CCA-14901g,06may05,tis add support for CCA-14601f,01feb05,tis intreduced GT_REG_CHAR_READ/GT_REG_CHAR_WRITE to read/write 8bits at a time PT#257001e,19nov04, tis -include gt644xx.h instead of gt64360r_dy4.h -include boardName.h01d,01nov04,tis add support for CCA-14501c,16sep04,mb PT 2180: replaced obsolete macro DISCO_SPACE_ADRS by CPU_DISCO2_BASE_ADRS01b,04feb02,tng add more structs and macros01a,20jan03,marvell derrive from BSP DB-64360 Ver 1.2/0.2-I*//*DESCRIPTIONThis header file contains simple read/write macros for addressingthe SDRAM, devices, GT`s internal registers and PCI (using the PCI`saddress space). The macros take care of Big/Little endian conversions. INCLUDE FILES: gt64360r_dy4.h, dy4182.h for DY4182 or gt644xx.h, cca145.h, cca146.h for CCA-146*/#ifndef __INCgtCoreh#define __INCgtCoreh/* includes */#include "h/drv/dy4/boardName.h"#ifdef VME_182#include "gt64360r_dy4.h"#include "dy4182.h"#endif#ifdef CCA_145#include "gt644xx.h"#include "cca145.h"#endif#ifdef CCA_146#include "gt644xx.h"#include "cca146.h"#endif#ifdef VME_183#include "gt644xx.h"#include "cwv183.h"#endif#ifdef SCP_124#include "gt644xx.h"#include "cwcp124.h"#endif#ifdef CCA_149#include "gt644xx.h"#include "cca149.h"#endif#ifdef __cplusplusextern "C" {#endif/* globals *//* Disco base address for reference only */;#define gtInternalRegBaseAddr CPU_DISCO2_BASE_ADRS/* typedefs */#ifndef __cplusplus typedef enum _bool {false,true} bool;#endif /* __cplusplus *//* defines *//****************************************//* GENERAL Definitions *//****************************************/#define NO_BIT 0x00000000#define BIT0 0x00000001#define BIT1 0x00000002#define BIT2 0x00000004#define BIT3 0x00000008#define BIT4 0x00000010#define BIT5 0x00000020#define BIT6 0x00000040#define BIT7 0x00000080#define BIT8 0x00000100#define BIT9 0x00000200#define BIT10 0x00000400#define BIT11 0x00000800#define BIT12 0x00001000#define BIT13 0x00002000#define BIT14 0x00004000#define BIT15 0x00008000#define BIT16 0x00010000#define BIT17 0x00020000#define BIT18 0x00040000#define BIT19 0x00080000#define BIT20 0x00100000#define BIT21 0x00200000#define BIT22 0x00400000#define BIT23 0x00800000#define BIT24 0x01000000#define BIT25 0x02000000#define BIT26 0x04000000#define BIT27 0x08000000#define BIT28 0x10000000#define BIT29 0x20000000#define BIT30 0x40000000#define BIT31 0x80000000 /* Size defintions */#define _1K 0x00000400#define _2K 0x00000800#define _4K 0x00001000#define _8K 0x00002000#define _16K 0x00004000#define _32K 0x00008000#define _64K 0x00010000#define _128K 0x00020000#define _256K 0x00040000#define _512K 0x00080000#define _1M 0x00100000#define _2M 0x00200000#define _3M 0x00300000#define _4M 0x00400000#define _5M 0x00500000#define _6M 0x00600000#define _7M 0x00700000#define _8M 0x00800000#define _9M 0x00900000#define _10M 0x00a00000#define _11M 0x00b00000#define _12M 0x00c00000#define _13M 0x00d00000#define _14M 0x00e00000#define _15M 0x00f00000#define _16M 0x01000000#define _32M 0x02000000#ifndef NULL #define NULL 0#endif /* NULL *//* Little to Big endian conversion macros */#ifdef LE /* Little Endian */ #define GT_SHORT_SWAP(X) (X) #define GT_WORD_SWAP(X) (X) #define GT_LONG_SWAP(X) ((l64)(X))#else /* Big Endian */ #if (!defined(GT_SHORT_SWAP) && !defined(__USING_GNU_PPC__)) #define GT_SHORT_SWAP(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) #endif /* GT_SHORT_SWAP */ #if (!defined(GT_WORD_SWAP) && !defined(__USING_GNU_PPC__)) #define GT_WORD_SWAP(X) ((((X)&0xff)<<24) | \ (((X)&0xff00)<<8) | \ (((X)&0xff0000)>>8) | \ (((X)&0xff000000)>>24)) #endif /* GT_WORD_SWAP */ #if !defined(GT_LONG_SWAP) #define GT_LONG_SWAP(X) ((l64) ((((X)&0xffULL)<<56) | \ (((X)&0xff00ULL)<<40) | \ (((X)&0xff0000ULL)<<24) | \ (((X)&0xff000000ULL)<<8) | \ (((X)&0xff00000000ULL)>>8) | \ (((X)&0xff0000000000ULL)>>24) | \ (((X)&0xff000000000000ULL)>>40) | \ (((X)&0xff00000000000000ULL)>>56))) #endif /* GT_LONG_SWAP */#endif /* LE */
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