gti2c.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* gtI2c.h - Header File for Discovery I2C definitions and function declarations. */

/**************************************************************************
 *
 *   Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights
 *   reserved.  This Source Code is the Property of Curtiss-Wright
 *   Controls, Inc. and can only be used in accordance with Source
 *   Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any
 *   of its subsidiaries.
 *
 **************************************************************************/

/* Copyright 1984 - 1997 Wind River Systems, Inc. */

/*
modification history
--------------------
01g,08dec05, tis        rename Discovery_II directory to Discovery_III CR#12835.
01f,05dec05, asu        changed I2C_FREQ to 50Khz
01e,04oct05, asu        add support for I2C_RLTEMP2_SENS, for second MAX1617 device
			CCA_149
01d,11aug05, tis        changed I2C_FREQ to 90Khz
                        added the functions dy4I2cSetAckBitClearIntFlag() and
                        dy4I2cClearAckAndIntBits()CR#11550
01c,26may05, tis        add support for new 146 I2c devices(I2C_ETR, I2C_RLTEMP_SENS).
01b,13apr04, mb         Renamed the typedef enums for I2C_STATUS
01a,28may03, rgs        Standard file header added
*/

/*
DESCRIPTION:
Function to control the I2C unit.

INCLUDE FILES: h/drv/discovery_II/gtCore_dy4.h

SEE ALSO:
*/


/*******************************************************************************
*                   Copyright 2002, GALILEO TECHNOLOGY, LTD.                   *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*                                                                              *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
*******************************************************************************/


#ifndef __INCgtI2ch 
#define __INCgtI2ch
#ifdef __cplusplus
extern "C" {
#endif

/* includes */
#include "h/drv/dy4/boardName.h"
#if defined (SCP_124) || defined (VME_183)
#include "h/drv/discovery_III/gtCore_dy4.h"
#else
#include "h/drv/discovery_II/gtCore_dy4.h"
#endif
/* defines */
#define I2C_FREQ                        50000      /* 50 KHz */

#define I2C_TIMEOUT_VALUE               0x1000   
#define I2C_ENABLE                      BIT6
#define I2C_INT_ENABLE                  BIT7
#define I2C_ACK                         BIT2
#define I2C_INT_FLAG                    BIT3
#define I2C_STOP_BIT                    BIT4
#define I2C_START_BIT                   BIT5 
#define I2C_READ                        BIT0
#define I2C_WRITE                       0

#define I2C_EEPROM_DELAY                10 /* Mili sec */
#define I2C_10BIT_ADDR                  BIT31

/* I2C status codes */
/*  ShogtRtcuts-
    RECEIVED    -> REC
    TRANSMITED  -> TRA
    MASTER      -> MAS
    SLAVE       -> SLA
    ACKNOWLEDGE -> ACK
    ARBITRATION -> ARB
    ADDR        -> ADDR
*/

#define I2C_BUS_ERROR                                                       0X00
#define I2C_START_CONDITION_TRA                                             0X08
#define I2C_REPEATED_START_CONDITION_TRA                                    0X10
#define I2C_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC                                 0X18
#define I2C_ADDR_PLUS_WRITE_BIT_TRA_ACK_NOT_REC                             0X20
#define I2C_MAS_TRAN_DATA_BYTE_ACK_REC                                      0X28
#define I2C_MAS_TRAN_DATA_BYTE_ACK_NOT_REC                                  0X30
#define I2C_MAS_LOST_ARB_DURING_ADDR_OR_DATA_TRA                            0X38
#define I2C_ADDR_PLUS_READ_BIT_TRA_ACK_REC                                  0X40
#define I2C_ADDR_PLUS_READ_BIT_TRA_ACK_NOT_REC                              0X48
#define I2C_MAS_REC_READ_DATA_ACK_TRA                                       0X50
#define I2C_MAS_REC_READ_DATA_ACK_NOT_TRA                                   0X58
#define I2C_SLA_REC_ADDR_PLUS_WRITE_BIT_ACK_TRA                             0X60
#define I2C_MAS_LOST_ARB_DURING_ADDR_TRA_ADDR_IS_TARGETED_TO_SLA_ACK_TRA_W  0X68
#define I2C_GENERAL_CALL_REC_ACK_TRA                                        0X70
#define I2C_MAS_LOST_ARB_DURING_ADDR_TRA_GENERAL_CALL_ADDR_REC_ACK_TRA      0X78
#define I2C_SLA_REC_WRITE_DATA_AFTER_REC_SLA_ADDR_ACK_TRAN                  0X80
#define I2C_SLA_REC_WRITE_DATA_AFTER_REC_SLA_ADDR_ACK_NOT_TRAN              0X88
#define I2C_SLA_REC_WRITE_DATA_AFTER_REC_GENERAL_CALL_ACK_TRAN              0X90
#define I2C_SLA_REC_WRITE_DATA_AFTER_REC_GENERAL_CALL_ACK_NOT_TRAN          0X98
#define I2C_SLA_REC_STOP_OR_REPEATED_START_CONDITION                        0XA0
#define I2C_SLA_REC_ADDR_PLUS_READ_BIT_ACK_TRA                              0XA8
#define I2C_MAS_LOST_ARB_DURING_ADDR_TRA_ADDR_IS_TARGETED_TO_SLA_ACK_TRA_R  0XB0
#define I2C_SLA_TRA_READ_DATA_ACK_REC                                       0XB8
#define I2C_SLA_TRA_READ_DATA_ACK_NOT_REC                                   0XC0
#define I2C_SLA_TRA_LAST_READ_DATA_ACK_REC                                  0XC8
#define I2C_SECOND_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC                          0XD0
#define I2C_SECOND_ADDR_PLUS_WRITE_BIT_TRA_ACK_NOT_REC                      0XD8
#define I2C_SECOND_ADDR_PLUS_READ_BIT_TRA_ACK_REC                           0XE0
#define I2C_SECOND_ADDR_PLUS_READ_BIT_TRA_ACK_NOT_REC                       0XE8
#define I2C_NO_RELEVANT_STATUS_INTERRUPT_FLAG_IS_KEPT_0                     0XF8

/* typedefs */

typedef enum i2cStartType
{
    I2C_FIRST_START,
    I2C_REPEATED_START
} I2C_START_TYPE;

typedef enum i2cCheckType
{
    I2C_WRITE_CHECK,
    I2C_READ_CHECK,
    I2C_DATA_CHECK,
    I2C_START_CHECK
} I2C_CHECK_TYPE;

typedef enum i2cDevType
{
    I2C_TEMP_SENS,
    I2C_EEPROM,
    I2C_RLTEMP_SENS,
    I2C_RLTEMP2_SENS,
    I2C_ETR
} I2C_DEV_TYPE;

typedef enum i2cStatus
{
    STAT_I2C_OK,
    STAT_I2C_TIMEOUT,
    STAT_I2C_BUS_ERROR,
    STAT_I2C_ADDR_PLUS_WRITE_BIT_TRA_ACK_NOT_REC,
    STAT_I2C_MAS_TRAN_DATA_BYTE_ACK_NOT_REC,
    STAT_I2C_ADDR_PLUS_READ_BIT_TRA_ACK_NOT_REC,
    STAT_I2C_MAS_LOST_ARB_DURING_ADDR_TRA_ADDR_IS_TARGETED_TO_SLA_ACK_TRA_W,  
    STAT_I2C_MAS_LOST_ARB_DURING_ADDR_TRA_GENERAL_CALL_ADDR_REC_ACK_TRA,      
    STAT_I2C_SLA_REC_WRITE_DATA_AFTER_REC_SLA_ADDR_ACK_NOT_TRAN,              
    STAT_I2C_SLA_REC_WRITE_DATA_AFTER_REC_GENERAL_CALL_ACK_NOT_TRAN,          
    STAT_I2C_MAS_LOST_ARB_DURING_ADDR_TRA_ADDR_IS_TARGETED_TO_SLA_ACK_TRA_R,  
    STAT_I2C_SLA_TRA_READ_DATA_ACK_NOT_REC,                                   
    STAT_I2C_SECOND_ADDR_PLUS_WRITE_BIT_TRA_ACK_NOT_REC,                      
    STAT_I2C_SECOND_ADDR_PLUS_READ_BIT_TRA_ACK_NOT_REC,                       
    STAT_I2C_NO_RELEVANT_STATUS_INTERRUPT_FLAG_IS_KEPT_0,       
    STAT_I2C_UNKNOWN_DEVICE
} I2C_STATUS;

void dy4I2cMasterInit(void);
void dy4I2cIntEnable(void);
void dy4I2cIntDisable(void);
unsigned int dy4I2cReadStatus(void);
unsigned int dy4I2cReadIntFlag(void);
void dy4I2cClearIntFlag(void);
void dy4I2cReset(void);
I2C_STATUS dy4I2cStatusCheck(I2C_CHECK_TYPE checkType);
I2C_STATUS dy4I2cSetStartBit(I2C_START_TYPE startType);
void dy4I2cSetStopBit(void);
void dy4I2cSetAckBit(void);
void dy4I2cClearAckBit(void);
void dy4I2cDelay(unsigned int time);
I2C_STATUS dy4I2cMasterSendDeviceAddr(I2C_DEV_TYPE devType, unsigned int addr, unsigned int flag);
I2C_STATUS dy4I2cMasterRead(I2C_DEV_TYPE devType, 
                           unsigned int addr,
                           unsigned int offset, 
                           unsigned char *data, 
                           unsigned int size);
I2C_STATUS dy4I2cMasterSendOffset(I2C_DEV_TYPE devType,
                                 unsigned int addr, 
                                 unsigned offset);
I2C_STATUS dy4I2cMasterWrite(I2C_DEV_TYPE devType, 
                            unsigned int addr,
                            unsigned int offset, 
                            unsigned char *data,
                            unsigned int size); 
void dy4I2cSetAckBitClearIntFlag(void);
void dy4I2cClearAckAndIntBits(void);                            
#ifdef __cplusplus
}
#endif
#endif /* __INCgtI2ch */