gtdma_dy4.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* gtDma_dy4.h - Header File for Discovery DMA definitions and function declarations  */

/**************************************************************************
 *
 *   Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights
 *   reserved.  This Source Code is the Property of Curtiss-Wright
 *   Controls, Inc. and can only be used in accordance with Source
 *   Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any
 *   of its subsidiaries.
 *
 **************************************************************************/

/*******************************************************************************
*                   Copyright 2002, GALILEO TECHNOLOGY, LTD.                   *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*                                                                              *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
********************************************************************************/

/*
modification history
--------------------
01g,08dec05,tis    rename Discovery_II directory to Discovery_III CR#12835.
01f,20sep04,rcd    added legacy defines from gt64260.
01e,05aug04,rcd    update descriptions and added gtDmaTransfer2 to 
                   handle PPC endian correctly.
01d,30apr03,aak    update from BSP DB-64360 Ver 1.2/0.2-I
01c,12sep02,aak    add restriction description
01b,04feb02,aak    integrate into VME-181 BSP rel 0.2
01a,26sep01,marvell dma.h EV-64260A-BP BSP Version 2.2/1
*/

/*
DESCRIPTION

 This file introduces a complete interface to the on-chip DMA engines,
 including functions for controlling the DMA priority mechanism.                
 To fully understand the capabilities of the DMA engines please devote  
 some time to reviewing the Discovery chip spec.                                               

DEPENDENCIES: gtCore.h

*/

#ifndef __INCgtDmah
#define __INCgtDmah

/* includes */

#include "h/drv/dy4/boardName.h"
#if defined (SCP_124) || defined (VME_183)
#include "h/drv/discovery_III/gtCore_dy4.h"
#else
#include "h/drv/discovery_II/gtCore_dy4.h"
#endif /*SCP_124 */

#ifdef __cplusplus
extern "C" {
#endif


/* defines */
#define DMA_FIRST_ENGINE    DMA_ENG_0
#ifdef GT64260
#define DMA_LAST_ENGINE     DMA_ENG_7
#else
#define DMA_LAST_ENGINE     DMA_ENG_3
#endif

#define DMA_WIN_FIRST       DMA_WINDOW0
#define DMA_WIN_LAST        DMA_WINDOW7
#define MIN_DMA_WINDOW_SIZE 0x10000

#define IS_INVALID_ENGINE(engine)                                              \
                    ((engine) < DMA_FIRST_ENGINE || DMA_LAST_ENGINE < (engine))

/* Round-robin setting for pizza arbiter */
#define DMA_ROUND_ROBIN                             0xe4e4e4e4

/*  source DTLs */
#define DMA_DTL_8BYTES			                    NO_BIT
#define DMA_DTL_16BYTES			                    BIT6
#define DMA_DTL_32BYTES			                    (BIT6|BIT7)
#define DMA_DTL_64BYTES			                    (BIT6|BIT7|BIT8)
#define DMA_DTL_128BYTES                            BIT8

/* Destination DTL */
#define DMA_DEST_DTL_8BYTES			                BIT1
#define DMA_DEST_DTL_16BYTES		                BIT0
#define DMA_DEST_DTL_32BYTES		                (BIT0|BIT1)
#define DMA_DEST_DTL_64BYTES		                (BIT0|BIT1|BIT2)
#define DMA_DEST_DTL_128BYTES                       BIT2

/*
 * defines command for the LOW control register
 */

#define DMA_HOLD_SOURCE_ADDR		                BIT3
#define DMA_ACK_ASSERT_AFTER_TWO_TCLK               BIT4
#define DMA_HOLD_DEST_ADDR		                    BIT5
#define DMA_NON_CHAIN_MODE  		                BIT9
#define DMA_CHAIN_MODE  			                NO_BIT
#define DMA_INTERRUPT_EVERY_NULL_POINTER            BIT10
#define DMA_BLOCK_TRANSFER_MODE		                BIT11
#define DMA_DEMAND_MODE			                    NO_BIT
#define DMA_CHANNEL_ENABLE			                BIT12
#define DMA_FETCH_NEXT_RECORD		                BIT13
#define DMA_ACTIVITY_STATUS                         BIT14
#define DMA_REQ_DIRECTION_BY_SOURCE                 NO_BIT
#define DMA_REQ_DIRECTION_BY_DEST                   BIT15
#define DMA_REQ_IS_LEVEL_INPUT                      NO_BIT
#define DMA_REQ_IS_EDGE_TRIGGERD_INPUT              BIT16
#define DMA_CLOSE_DESCRIPTOR_ENABLE		            BIT17
#define DMA_ENABLE_EOT                              BIT18
#define DMA_FETCH_NEXT_DES_ON_EOT	                NO_BIT
#define DMA_CHANNEL_HALT_ON_EOT  	                BIT19
#define DMA_CHANNEL_ABORT		                    BIT20
/* Note: When using the source/destination address override
         feature , window 1 must be allocated for PCI0 and window 2
         must be allocated for PCI1 */
#define DMA_SOURCE_ADDR_IN_PCI0	                    BIT21
#define DMA_SOURCE_ADDR_IN_PCI1	                    BIT22
#define DMA_DEST_ADDR_IN_PCI0		                BIT23
#define DMA_DEST_ADDR_IN_PCI1		                BIT24
#define DMA_REC_ADDR_IN_PCI0		                BIT25
#define DMA_REC_ADDR_IN_PCI1		                BIT26
#define DMA_ACK_ASSERT_ONE_TCK_ON_TRAN              NO_BIT
#define DMA_ACK_ASSERT_ON_ACT_TRAN_ON_DEVICE_BUS    BIT27
#define DMA_REQ_FROM_DMA_REQ_PIN	                NO_BIT
#define DMA_REQ_FROM_TIMER_COUNTER	                BIT28
#define DMA_ACK_ASSERT_ON_ACCESS_TO_DEST            BIT29
#define DMA_ACK_ASSERT_ON_ACCESS_TO_SRC             BIT30
#define DMA_64K_DESCRIPTOR_MODE                     NO_BIT
#define DMA_16M_DESCRIPTOR_MODE                     BIT31


/*
 * defines command for the HIGH control register
 */

#define DMA_ENDIANESS		                BIT0
#define DMA_DESC_BS                             BIT1


/*
 *    Memory space attribute definitions   
 */
#define DMA_NO_ATTR                                 NO_BIT
#ifdef  INCLUDE_SNOOP_SUPPORT
    /* If the target interface of the region is DRAM bank,these attributes
       select whether its cache coherent or not (PPC only)*/
    #define DMA_WT_CACHE_COHERENT                   BIT12
    #define DMA_WB_CACHE_COHERENT                   BIT13
    /* PCI-X No Snoop (NS) attributes */
    #define DMA_NS_ATTR_IS_NOT_ASSERTED             NO_BIT
    #define DMA_NS_ATTR_IS_ASSERTED                 BIT10
#endif /* INCLUDE_SNOOP_SUPPORT */
/* If the target interface is PCI0 or PCI1 these definitions
       controls the data swap */
#define DMA_PCI_BYTE_SWAP                           NO_BIT
#define DMA_PCI_NO_SWAP                             BIT8
#define DMA_PCI_BYTE_AND_WORD_SWAP                  BIT9
#define DMA_PCI_WORD_SWAP                           (BIT9|BIT8)
/* These attributes select PCI I/O or memory space */
#define DMA_PCI_IO_SPACE                            NO_BIT
#define DMA_PCI_MEMORY_SPACE                        BIT11
/* These attributes control the PCI REQ64* mode  */
#define DMA_PCI_ALWAYS_ASSERT_REQ64                 NO_BIT
#define DMA_PCI_REQ64_ACCORDING_TO_DATA_SIZE        BIT12

/*
 * typedefs
 */
typedef enum _dmaEngine{
		DMA_ENG_0, DMA_ENG_1, DMA_ENG_2, DMA_ENG_3
#ifdef GT64260
		,DMA_ENG_4 ,DMA_ENG_5 ,DMA_ENG_6 ,DMA_ENG_7
#endif
} DMA_ENGINE;

/*
 * There are 8 regions that can be defind by base,
 * size and attributes. Each region can be associated
 * with a target interface (DRAM, DEVICE, SRAM...)
 */
typedef enum _dmaMemSpace{DMA_WINDOW0, DMA_WINDOW1, DMA_WINDOW2, DMA_WINDOW3,
                          DMA_WINDOW4, DMA_WINDOW5, DMA_WINDOW6, DMA_WINDOW7
                         } DMA_MEM_SPACE;

typedef enum _dmaMemSpaceTarget{DMA_DRAM_CS0 = BIT9|BIT10|BIT11,
                                DMA_DRAM_CS1 = BIT8|BIT10|BIT11,
                                DMA_DRAM_CS2 = BIT8|BIT9|BIT11,
                                DMA_DRAM_CS3 = BIT8|BIT9|BIT10,
                                DMA_DEV_CS0 = BIT9|BIT10|BIT11|BIT12|BIT0,
                                DMA_DEV_CS1 = BIT8|BIT10|BIT11|BIT12|BIT0,
                                DMA_DEV_CS2 = BIT8|BIT9|BIT11|BIT12|BIT0,
                                DMA_DEV_CS3 = BIT8|BIT9|BIT10|BIT12|BIT0,
                                DMA_DEV_BOOT = BIT8|BIT9|BIT10|BIT11|BIT0,
                                DMA_SRAM = BIT1,
#ifdef INCLUDE_CPU_MAPPING
                                DMA_60X_BUS = BIT11|BIT1,
#endif /* INCLUDE_CPU_MAPPING */
                                DMA_PCI_0 = BIT0|BIT1,
                                DMA_PCI_1 = BIT2
                               } DMA_MEM_SPACE_TARGET;

typedef enum _dmaMemSpaceAccess{DMA_NO_ACCESS = NO_BIT,
                                DMA_READ_ONLY = BIT0,
                                DMA_FULL_ACCESS = BIT0|BIT1
                               } DMA_MEM_SPACE_ACCESS;

/* status codes */
typedef enum _dmaStatus	{DMA_OK,
						DMA_CHANNEL_IDLE,
						DMA_CHANNEL_BUSY,
                        DMA_NO_SUCH_CHANNEL,
						DMA_GENERAL_ERROR
                       } DMA_STATUS;

/*******************************************************************************
*
*   Pizza arbiter slices Struct: Defined by user and used for updating the
*   DMA Arbiter with priority for each channel.
*   By default DMA_PIZZA is configured to ROUND_ROBIN.
*   Each field represent one of 16 slices, in order to configurate it to one
*   of the four engine simply write the engine number at the slice field.
*
*******************************************************************************/

typedef struct _dmaPizza0_3
{
    unsigned char slice0;
    unsigned char slice1;
    unsigned char slice2;
    unsigned char slice3;
    unsigned char slice4;
    unsigned char slice5;
    unsigned char slice6;
    unsigned char slice7;
    unsigned char slice8;
    unsigned char slice9;
    unsigned char slice10;
    unsigned char slice11;
    unsigned char slice12;
    unsigned char slice13;
    unsigned char slice14;
    unsigned char slice15;
} DMA_PIZZA0_3;

typedef struct _dmaPizza0_3 DMA_PIZZA;

#ifdef GT64260
typedef struct dmaPizza4_7
{
    unsigned char    slice0;
    unsigned char    slice1; 
    unsigned char    slice2;
    unsigned char    slice3;
    unsigned char    slice4;
    unsigned char    slice5;
    unsigned char    slice6;
    unsigned char    slice7;
    unsigned char    slice8;
    unsigned char    slice9;
    unsigned char    slice10;
    unsigned char    slice11;
    unsigned char    slice12;
    unsigned char    slice13;
    unsigned char    slice14;
    unsigned char    slice15;
} DMA_PIZZA4_7;
#endif

/* dma descriptor structure */
typedef struct _dmaRecord
{
    unsigned int ByteCnt;
    unsigned int SrcAdd;
    unsigned int DestAdd;
    unsigned int NextRecPtr;
} DMA_RECORD;


/*
 * Legacy defines from the Discovery 1:  GT64260
 */
#define DEST_DTL_8BYTES		    NO_BIT
#define DEST_DTL_16BYTES	    BIT0
#define DEST_DTL_32BYTES	    (BIT0 | BIT1)
#define DEST_DTL_64BYTES	    (BIT0 | BIT1 | BIT2)
#define DEST_DTL_128BYTES           BIT2
#define HOLD_SOURCE_ADDRESS	    BIT3
#define HOLD_DEST_ADDRESS	    BIT5
#define DTL_8BYTES		    NO_BIT
#define DTL_16BYTES		    BIT6
#define DTL_32BYTES		    (BIT6 | BIT7)
#define DTL_64BYTES		    (BIT6 | BIT7 | BIT8)
#define DTL_128BYTES                BIT8
#define NON_CHAIN_MODE  	    BIT9
#define CHAIN_MODE  		    NO_BIT
#define INT_EVERY_NULL_POINTER	    BIT10
#define BLOCK_TRANSFER_MODE	    BIT11
#define DEMAND_MODE		    NO_BIT
#define CHANNEL_ENABLE		    BIT12
#define FETCH_NEXT_RECORD	    BIT13
#define DMA_ACTIVITY_STATUS         BIT14
#define ALIGN_TOWARD_DEST	    BIT15
#define MASK_DMA_REQ		    BIT16
#define ENABLE_DESCRIPTOR	    BIT17
#define ENABLE_EOT		    BIT18
#define ENABLE_EOT_INTERRUPT	    BIT19
#define ABORT_DMA		    BIT20