gtdmaintcntrl_dy4.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* gtDmaIntCtrl_dy4.h - source file for the MV-64x60 DMA interrupt controller */

/**************************************************************************
 *
 *   Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights
 *   reserved.  This Source Code is the Property of Curtiss-Wright
 *   Controls, Inc. and can only be used in accordance with Source
 *   Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any
 *   of its subsidiaries.
 *
 **************************************************************************/



/*******************************************************************************
*                   Copyright 2002, GALILEO TECHNOLOGY, LTD.                   *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*                                                                              *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
********************************************************************************/
/*
modification history
--------------------
01h,06dec05,tis         add support for SCP-124
01g,29sep05,asu         add support for CCA-149
01f,06may05,tis         add support for CCA-146
01e,01nov04,tis         add support for CCA-145
01d,14oct04,mb          PT 2174: added prototype for gtDmaIntAck function
01c,20sep04,rcd         added legacy defines from gt64260.
01b,09apr03,aak         integarte into 182 BSP
01a,20jan03,marvell     derrived from BSP DB-64360 Ver 1.2/0.2-I
*/

#ifndef __INCvxDmaIntCtrlh
#define __INCvxDmaIntCtrlh

/* includes */
#include "h/drv/dy4/boardName.h"

#ifdef VME_182
#include "intCtrl182_dy4.h"
#endif
#ifdef CCA_145
#include "intCtrl145.h"
#endif
#ifdef CCA_146
#include "intCtrl146.h"
#endif
#ifdef CCA_149
#include "intCtrl149.h"
#endif
#ifdef VME_183
#include "intCtrl183.h"
#endif

#ifdef SCP_124
#include "intCtrl124.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif

/* defines  */

/* typedefs */
typedef struct _gtIsrEntry {
    UINT        causeBit;  /* A specific cause bit in the cause register.*/
    VOIDFUNCPTR userISR;   /* A user ISR pointer.*/
    int         arg;       /* An argument to interrupt ISR. */
    int         prio;      /* An interrupt priority. */
} GT_ISR_ENTRY;

/* DMA_CAUSE is an enumerator that moves between 0 and 31. This enumerator */
/* describes the cause bits positions in the DMA cause  registers.         */

typedef enum _dmaCause
{
    /* DMA channels 0-3 Interrupt cause register (0x8c0) */
    DMA_CAUSE_START = -1, /* Cause Start boundry */
    DMA_CHAN0_COMP      , /* Channel0 DMA Completion.                        */
    DMA_CHAN0_ADDR_MISS , /* Channel0 Address Miss / Failed address decoding.*/
    DMA_CHAN0_ACC_PROT  , /* Channel0 Access Protect Violation               */
    DMA_CHAN0_WR_PROT   , /* Channel0 Write Protect Violation                */
    DMA_CHAN0_OWN       , /* Channel0 Descriptor Ownership Violation         */
    DMA_RSRVD_L05       ,
    DMA_RSRVD_L06       ,
    DMA_RSRVD_L07       ,
    DMA_CHAN1_COMP      , /* Channel1 DMA Completion.                        */
    DMA_CHAN1_ADDR_MISS , /* Channel1 Address Miss / Failed address decoding.*/
    DMA_CHAN1_ACC_PROT  , /* Channel1 Access Protect Violation               */
    DMA_CHAN1_WR_PROT   , /* Channel1 Write Protect Violation                */
    DMA_CHAN1_OWN       , /* Channel1 Descriptor Ownership Violation         */
    DMA_RSRVD_L13       ,
    DMA_RSRVD_L14       ,
    DMA_RSRVD_L15       ,
    DMA_CHAN2_COMP      , /* Channel2 DMA Completion.                        */
    DMA_CHAN2_ADDR_MISS , /* Channel2 Address Miss / Failed address decoding.*/
    DMA_CHAN2_ACC_PROT  , /* Channel2 Access Protect Violation               */
    DMA_CHAN2_WR_PROT   , /* Channel2 Write Protect Violation                */
    DMA_CHAN2_OWN       , /* Channel2 Descriptor Ownership Violation         */
    DMA_CHAN2_L21       ,
    DMA_RSRVD_L22       ,
    DMA_RSRVD_L23       ,
    DMA_CHAN3_COMP      , /* Channel3 DMA Completion.                        */
    DMA_CHAN3_ADDR_MISS , /* Channel3 Address Miss / Failed address decoding.*/
    DMA_CHAN3_ACC_PROT  , /* Channel3 Access Protect Violation               */
    DMA_CHAN3_WR_PROT   , /* Channel3 Write Protect Violation                */
    DMA_CHAN3_OWN       , /* Channel3 Descriptor Ownership Violation         */
    DMA_RSRVD_L29       ,
    DMA_RSRVD_L30       ,
    DMA_RSRVD_L31       ,
    DMA_CAUSE_END   /* Cause End boundry */
} DMA_CAUSE;

/* Legacy defines from the discovery 1: GT-64260 */

#define    DMA_CHAN0_COMPLETION                      	DMA_CHAN0_COMP
#define    DMA_CHAN0_ADDRESS_MISS                      	DMA_CHAN0_ADDR_MISS 
#define    DMA_CHAN0_ACCESS_PROTECT_VIOLATION          	DMA_CHAN0_ACC_PROT  
#define    DMA_CHAN0_WRITE_PROTECT                     	DMA_CHAN0_WR_PROT   
#define    DMA_CHAN0_DESCRIPTOR_OWNERSHIP_VIOLATION    	DMA_CHAN0_OWN       

#define    DMA_CHAN1_COMPLETION                        	DMA_CHAN1_COMP
#define    DMA_CHAN1_ADDRESS_MISS                      	DMA_CHAN1_ADDR_MISS 
#define    DMA_CHAN1_ACCESS_PROTECT_VIOLATION          	DMA_CHAN1_ACC_PROT  
#define    DMA_CHAN1_WRITE_PROTECT                     	DMA_CHAN1_WR_PROT   
#define    DMA_CHAN1_DESCRIPTOR_OWNERSHIP_VIOLATION    	DMA_CHAN1_OWN    

#define    DMA_CHAN2_COMPLETION                        	DMA_CHAN2_COMP      
#define    DMA_CHAN2_ADDRESS_MISS                     	DMA_CHAN2_ADDR_MISS 
#define    DMA_CHAN2_ACCESS_PROTECT_VIOLATION          	DMA_CHAN2_ACC_PROT  
#define    DMA_CHAN2_WRITE_PROTECT                     	DMA_CHAN2_WR_PROT   
#define    DMA_CHAN2_DESCRIPTOR_OWNERSHIP_VIOLATION   	DMA_CHAN2_OWN       

#define    DMA_CHAN3_COMPLETION                       	DMA_CHAN3_COMP      
#define    DMA_CHAN3_ADDRESS_MISS                    	DMA_CHAN3_ADDR_MISS 
#define    DMA_CHAN3_ACCESS_PROTECT_VIOLATION        	DMA_CHAN3_ACC_PROT  
#define    DMA_CHAN3_WRITE_PROTECT                   	DMA_CHAN3_WR_PROT   
#define    DMA_CHAN3_DESCRIPTOR_OWNERSHIP_VIOLATION   	DMA_CHAN3_OWN       


/* vxDmaIntCtrl.h API list */
void    gtDmaIntCtrlInit (void);
STATUS  gtDmaIntConnect  (DMA_CAUSE cause, VOIDFUNCPTR routine,
                          int parameter, int prio);
STATUS  gtDmaIntEnable   (DMA_CAUSE cause);
STATUS  gtDmaIntDisable  (DMA_CAUSE cause);
void    gtDmaIntAck      (DMA_CAUSE cause);


#ifdef __cplusplus
}
#endif

#endif /* __INCvxDmaIntCtrlh */