brg_dy4.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* brg_dy4.h - Baud Rate Generator library header File for GT-64X60 */

/**************************************************************************
 *
 *   Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights
 *   reserved.  This Source Code is the Property of Curtiss-Wright
 *   Controls, Inc. and can only be used in accordance with Source
 *   Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any
 *   of its subsidiaries.
 *
 **************************************************************************/

/*******************************************************************************
*                   Copyright 2002, GALILEO TECHNOLOGY, LTD.                   *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*                                                                              *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
********************************************************************************/
/*
modification history
--------------------
01e,06dec05,tis         -add support for SCP-124
                        -rename Discovery_II directory to Discovery_III CR#12835.
01d,26sep05,asu         add support for CCA-149
01c,06may05,tis         add support for CCA-146
01b,01nov04,tis         add support for CCA-145
01a,07may03,aak		derrive from VME-181 BSP rel 1.3
*/



#ifndef __INCbrgh
#define __INCbrgh

#include "h/drv/dy4/boardName.h"
#ifdef VME_182
#include "dy4182.h"
#endif

#ifdef CCA_145
#include "cca145.h"
#endif

#ifdef CCA_146
#include "cca146.h"
#endif

#ifdef CCA_149
#include "cca149.h"
#endif

#ifdef VME_183
#include "cwv183.h"
#endif

#ifdef SCP_124
#include "cwcp124.h"
#endif

#if defined(SCP_124) || defined(VME_183) 
#include "h/drv/discovery_III/gtCore_dy4.h"
#else
#include "h/drv/discovery_II/gtCore_dy4.h"
#endif

#ifdef __cplusplus
extern "C" {
#endif

/* defines  */

/* BRG Config Defines */

#define BRG_CDV_MASK                    0x0000ffff
#define BRG_ENABLE                      (1<<16)
#define BRG_RESET                       (1<<17)

/* BRG Clock Sources */
#define BRG_CLK_SRC_MASK                (UINT32)(0x1f<<18)
#define BRG_B_CLK_IN                    0x00
#define BRG_S_CLK_0                     0x02
#define BRG_TS_CLK_0                    0x03
#define BRG_S_CLK_1                     0x06
#define BRG_TS_CLK_1                    0x07
#define BRG_T_CLK                       0x08

#define BRG_CLKS                        18

#define BRG_BAUD_TUNING_SET(t,n)   GT_REG_WRITE (BRG_BAUDE_TUNING_REG(n),*((UINT32*)t))
#define BRG_BAUD_TUNING_GET(t,n)   GT_REG_READ(BRG_BAUDE_TUNING_REG(n),(UINT32*)t)
#define BRG_CONFIG_SET(c,n) 		GT_REG_WRITE( BRG_CONFIG_REG(n),*((UINT32*)c))
#define BRG_CONFIG_GET(c,n) 		GT_REG_READ( BRG_CONFIG_REG(n),(UINT32*)c )

/* BRG Configuration Register (BCR) */
#define BCR_CDV_MASK                0x0000FFFF
#define BCR_EN_ENABLE_BRG           0x00010000
#define BCR_RST_RESET_BRG           0x00020000
#define BRG_CLK_SRC_BCLKIN          0x00000000
#define BRG_CLK_SRC_SCLK0           0x00080000
#define BRG_CLK_SRC_TSCLK0          0x000c0000
#define BRG_CLK_SRC_SCLK1           0x00180000
#define BRG_CLK_SRC_TSCLK1          0x001c0000
#define BRG_CLK_SRC_SYSCLK          0x00200000

#define BRG_MAX_CDV					0x0000FFFF

/* typedefs */

/* typedefs */
typedef struct BRG_CONFIGION_AND_TUNING
{
    UINT32      config;
    UINT32      tuning;

} BRG_CONFIG_TUNING;


typedef enum _brgNum
{
	BRG_0,
	BRG_1
} BRG_NUM;

typedef enum _brgClkSrc
{
	BCLKIN,
	SCLK0 ,
	TSCLK0,
	SCLK1 ,
	TSCLK1,
	SYSCLK

} BRG_CLK_SRC;

/* #define BRG_CLK_SRC MPSC_BRG_CLOCK_SOURCE */

typedef struct
{
    BRG_NUM             brgNum;         /* Number of BRG. See BRG_NUM  		 */
    BRG_CLK_SRC         brgSrcClk;  	/* BRG clock source. See BRG_CLK_SRC */
    unsigned int        brgSrcClkRate;	/* Clock source rate.				 */
    unsigned int        brgConfigReg;  	/* BRG configuration register value	 */
} BRG_ENGINE;


void    brgInit  (BRG_ENGINE *pBrg);
void    brgStart (BRG_ENGINE *pBrg);
void    brgSetCdv(BRG_ENGINE *pBrg, unsigned short brgCdv);
STATUS  brgSetConfig (BRG_CONFIG_TUNING* brgConfig, UINT32 brgNumber);
STATUS  brgGetConfig (BRG_CONFIG_TUNING* brgConfig, UINT32 brgNumber);

#ifdef __cplusplus
}
#endif

#endif /* __INCbrgh */