gtmpsc.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

#define	 MPSC_END_INTERMEDIATE_BLOCK		            0x1F
#define	 MPSC_ENQUIRY						            0x5
#define	 MPSC_NACK							            0x15
#define	 MPSC_NULL_VALUE					            0x0
#define  MPSC_BISYNC_DEFAULT_SYNC_CHAR		            0x16
#define  MPSC_BISYNC_DEFAULT_DELIMETER_CHAR	            0x10

/* Const for BISYNC comm with odd parity */
#define  MPSC_START_OF_TXT_ODD					        0x2
#define	 MPSC_END_OF_TXT_ODD	   				        0x83
#define	 MPSC_START_OF_HNDLR_ODD				        0x1
#define	 MPSC_END_INTERMEDIATE_BLOCK_ODD		        0x1F
#define	 MPSC_ENQUIRY_ODD						        0x85
#define	 MPSC_NACK_ODD							        0x15
#define	 MPSC_NULL_VALUE_ODD					        0x80
#define  MPSC_BISYNC_DEFAULT_SYNC_CHAR_ODD		        0x16
#define  MPSC_BISYNC_DEFAULT_DELIMETER_CHAR_ODD	        0x10
                                                       
/* Const for BISYNC comm with even parity */           
#define  MPSC_START_OF_TXT_EVEN					        0x82
#define	 MPSC_END_OF_TXT_EVEN     				        0x3
#define	 MPSC_START_OF_HNDLR_EVEN				        0x81
#define	 MPSC_END_INTERMEDIATE_BLOCK_EVEN		       	0x9F
#define	 MPSC_ENQUIRY_EVEN						        0x5
#define	 MPSC_NACK_EVEN							        0x95
#define	 MPSC_NULL_VALUE_EVEN					        0x0
#define  MPSC_BISYNC_DEFAULT_SYNC_CHAR_EVEN		        0x96
#define  MPSC_BISYNC_DEFAULT_DELIMETER_CHAR_EVEN        0x90

/* set CHAR field, bits 7:0 */
#define GT_MPSC_BISYNC_CONTROL_CHAR_LOW(value) ((value) & 0xffff)
/* set CHAR field, bits 23:16 */
#define GT_MPSC_BISYNC_CONTROL_CHAR_HIGH(value) (((value) & 0xffff) << 16)

/* End of CHR5-8 defines */

/* Channel Register CHR10 for BISYNC */
#define  MPSC_BISYNC_CLEAR_TO_SEND						BIT0
#define  MPSC_BISYNC_CARRIER_DETECT						BIT1
#define  MPSC_BISYNC_TX_IN_IDLE							BIT3
#define  MPSC_BISYNC_RX_IN_HUNT							BIT5
#define  MPSC_BISYNC_RX_IN_IDLE							BIT11
#define  MPSC_BISYNC_DPLL_CARRIER_SENS					BIT12
#define  MPSC_BISYNC_RX_CONTROL_CHAR_1					BIT16
#define  MPSC_BISYNC_RX_CONTROL_CHAR_2					BIT17
#define  MPSC_BISYNC_RX_CONTROL_CHAR_3					BIT18
#define  MPSC_BISYNC_RX_CONTROL_CHAR_4					BIT19
#define  MPSC_BISYNC_RX_CONTROL_CHAR_5					BIT20
#define  MPSC_BISYNC_RX_CONTROL_CHAR_6					BIT21
#define  MPSC_BISYNC_RX_CONTROL_CHAR_7					BIT22
#define  MPSC_BISYNC_RX_CONTROL_CHAR_8					BIT23

/* End of CHR10 defines */

/***************************************************************************
*
*			UART DEFINITIONS
*
***************************************************************************/

/* MPSCx Protocol Configuration Register (MPCRx) for UART */
#define  MPSC_UART_DISABLE_RX_ON_TX				        BIT6
#define  MPSC_UART_ASYNCHRONOUS_MODE			        0
#define  MPSC_UART_ISOCHRONOUS_MODE  			        BIT7
#define  MPSC_UART_RX_ZERO_STOP_BIT				        BIT8
#define  MPSC_UART_FREEZE_TX					        BIT9
#define  MPSC_UART_NORMAL_MODE					        0
#define  MPSC_UART_MULTI_DROP_MODE				        BIT10
#define  MPSC_UART_CHAR_LENGTH_5_BIT			        0
#define  MPSC_UART_CHAR_LENGTH_6_BIT			        BIT12
#define  MPSC_UART_CHAR_LENGTH_7_BIT			        BIT13
#define  MPSC_UART_CHAR_LENGTH_8_BIT			        (BIT13 | BIT12)
#define  MPSC_UART_STOP_BIT_LENGTH_1			        0
#define  MPSC_UART_STOP_BIT_LENGTH_2			        BIT14
#define  MPSC_UART_FLOW_CONTROL_NORMAL			        0
#define  MPSC_UART_FLOW_CONTROL_ASYNC			        BIT15

/* End of MPCRx defines */

/* Channel Register CHR1 for UART */
/* bits' shift to BRK field */
#define MPSC_UART_BREAK_COUNT_SHIFT				        16
/* set TCS field */
#define GT_MPSC_UART_CONTROL_STUFF_CHAR(value) ((value) & 0xff)
/* set BRK field */
#define GT_MPSC_UART_BREAK_COUNT(value)							            \
		    (((value) & 0xff) << MPSC_UART_BREAK_COUNT_SHIFT)

/* End of CHR1 defines */

/* Channel Register CHR2 for UART */
#define  MPSC_UART_TX_ENABLE_VERTICAL_PARITY_CHECK		BIT1
#define  MPSC_UART_TX_PARITY_ODD						0
#define  MPSC_UART_TX_PARITY_LOW						BIT2
#define  MPSC_UART_TX_PARITY_EVEN						BIT3
#define  MPSC_UART_TX_PARITY_HIGH						(BIT3 | BIT2)
#define  MPSC_UART_ABORT_TX								BIT7
#define  MPSC_UART_TX_TCS_CHAR							BIT9
#define  MPSC_UART_RX_ENABLE_VERTICAL_PARITY_CHECK		BIT17
#define  MPSC_UART_RX_PARITY_ODD						0
#define  MPSC_UART_RX_PARITY_LOW						BIT18
#define  MPSC_UART_RX_PARITY_EVEN						BIT19
#define  MPSC_UART_RX_PARITY_HIGH						(BIT19 | BIT18)
#define  MPSC_UART_ABORT_RX								BIT23
#define  MPSC_UART_CLOSE_RX_DESCRIPTOR					BIT25
#define  MPSC_UART_ENTER_HUNT							BIT31

/* End of CHR2 defines */

/* Channel Register CHR3 for UART */
/* set Max Idle field */
#define GT_MPSC_UART_MAX_IDLE(value) ((value) & 0xffff)

/* End of CHR3 defines */

/* Channel Register CHR4 for UART */
/* set BCE field */
#define GT_MPSC_UART_CONTROL_FILTERING(value) ((value) & 0xff)

/* End of CHR4 defines */

/* Channel Registers CHR5-8 for UART */
#define  MPSC_UART_GENERATE_INTERRUPT_ON_RX				BIT12
#define  MPSC_UART_CONTROL_OCTET						BIT13
#define  MPSC_UART_REJECT_CHAR							BIT14
#define  MPSC_UART_ENTRY_NOT_VALID						0
#define  MPSC_UART_ENTRY_VALID							BIT15
/* set CHAR field, bits 7:0 */
#define GT_MPSC_UART_CONTROL_CHAR_LOW(value) ((value) & 0xffff)
/* set CHAR field, bits 23:16 */
#define GT_MPSC_UART_CONTROL_CHAR_HIGH(value) (((value) & 0xffff) << 16)

/* End of CHR5-8 defines */

/* Channel Register CHR9 for UART */
#define  MPSC_UART_MATCH_ADDRESS_1						BIT15
#define  MPSC_UART_MATCH_ADDRESS_2						BIT31
#define  GT_MPSC_UART_MATCH_ADDR_1(value)               ((value) & 0xff)
#define  GT_MPSC_UART_MATCH_ADDR_2(value)               (((value) & 0xff) << 16)

/* End of CHR9 defines */

/* Channel Register CHR10 for UART */
#define  MPSC_UART_CLEAR_TO_SEND						BIT0
#define  MPSC_UART_CARRIER_DETECT						BIT1
#define  MPSC_UART_TX_IN_IDLE							BIT3
#define  MPSC_UART_RX_IN_HUNT							BIT5
#define  MPSC_UART_RX_LINE_STATUS						BIT7
#define  MPSC_UART_RX_IN_IDLE							BIT11
#define  MPSC_UART_RX_CONTROL_CHAR_1					BIT16
#define  MPSC_UART_RX_CONTROL_CHAR_2					BIT17
#define  MPSC_UART_RX_CONTROL_CHAR_3					BIT18
#define  MPSC_UART_RX_CONTROL_CHAR_4					BIT19
#define  MPSC_UART_RX_CONTROL_CHAR_5					BIT20
#define  MPSC_UART_RX_CONTROL_CHAR_6					BIT21
#define  MPSC_UART_RX_CONTROL_CHAR_7					BIT22
#define  MPSC_UART_RX_CONTROL_CHAR_8					BIT23

/* End of CHR10 defines*/


/***************************************************************************
*
*			TRANSPARENT DEFINITIONS
*
***************************************************************************/

/* Channel Register CHR1 for TRANSPARENT */
#define  MPSC_TRANSPARENT_SYNC_MODE				        BIT15
#define  MPSC_TRANS_DEFAULT_SYNC_CHAR			        0x7E
/* set SYNC field 7:0 */
#define GT_MPSC_TRANSPARENT_SYNC_CHAR(value) ((value) & 0xff)
			
/* End of CHR1 defines */

/* Channel Register CHR2 for TRANSPARENT */
#define  MPSC_TRANSPARENT_ABORT_TX				        BIT7
#define  MPSC_TRANSPARENT_ABORT_RX				        BIT23
#define  MPSC_TRANSPARENT_CLOSE_RX_DESC			        BIT25
#define  MPSC_TRANSPARENT_ENTER_HUNT			        BIT31
                                                     
/* End of CHR2 defines */                             
                                                     
/* Channel Registers CHR10 for TRANSPARENT */        
#define  MPSC_TRANSPARENT_CLEAR_TO_SEND			        BIT0
#define  MPSC_TRANSPARENT_CARRIER_DETECT		        BIT1
#define  MPSC_TRANSPARENT_TX_IN_IDLE			        BIT3
#define  MPSC_TRANSPARENT_RX_IN_HUNT			        BIT5
#define  MPSC_TRANSPARENT_DPLL_CARRIER_SENSE	        BIT12

/* End of CHR10 defines */

/***************************************************************************
*
*			BRG Definitions
*
***************************************************************************/
/* defines for initialze BCR */
#define MPSC_ENABLE_BRG                                 BIT16
#define MPSC_RESET_BRG                                  BIT17
#define MPSC_BRG_BAUD_TUNING                            BIT25
#define MPSC_CDV_MASK                                   0x0000ffff


/* functions */
                     
void         gtMpscConfigForHDLC(MPSC_PORT port, MPSC_CLOCK_SOURCE rxClkSrc, 
                                 unsigned int rxClkRate, 
                                 MPSC_CLOCK_SOURCE txClkSrc,
                                 unsigned int txClkRate, unsigned int tclkFreq,
                                 MPSC_ACTUAL_RATES *rates);
void         gtMpscConfigForUART(MPSC_PORT port, MPSC_CLOCK_SOURCE rxClkSrc, 
                                 unsigned int rxClkRate, 
                                 MPSC_CLOCK_SOURCE txClkSrc,
                                 unsigned int txClkRate, unsigned int tclkFreq,
                                 MPSC_ACTUAL_RATES *rates);
void         gtMpscConfigForTRANSPARENT(MPSC_PORT port, 
                                        MPSC_CLOCK_SOURCE rxClkSrc, 
                                        unsigned int rxClkRate, 
                                        MPSC_CLOCK_SOURCE txClkSrc,
                                        unsigned int txClkRate, 
                                        unsigned int tclkFreq,
                                        MPSC_ACTUAL_RATES *rates);
void         gtMpscBrgEnable(MPSC_BRG_NUM brgNum);
void         gtMpscBrgDisable(MPSC_BRG_NUM brgNum);
unsigned int gtMpscBrgInit(MPSC_BRG_NUM brgNum, 
                           MPSC_BRG_CLOCK_SOURCE brgClockSource,
                           unsigned int brgClockSourceFreq, unsigned int freq);
void         gtAbortMpsc(MPSC_PORT port);
void         gtAbortAllMpscPorts();

#endif /* _INCgtmpsch */