📄 gtmpsc.h
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#define MPSC_TRANSMIT_IDLES BIT16#define MPSC_RTS_MODE_0 0#define MPSC_RTS_MODE_1 BIT17#define MPSC_CTS_SAMPLING_MODE_ASYNCHRONOUS 0#define MPSC_CTS_SAMPLING_MODE_SYNCHRONOUS BIT19#define MPSC_CD_SAMPLING_MODE_ASYNCHRONOUS 0#define MPSC_CD_SAMPLING_MODE_SYNCHRONOUS BIT20#define MPSC_CTS_ENVELOP_MODE 0#define MPSC_CTS_PULSE_MODE BIT21#define MPSC_CD_ENVELOP_MODE 0#define MPSC_CD_PULSE_MODE BIT22#define MPSC_CRC16_CCITT 0#define MPSC_CRC16 BIT23#define MPSC_CRC32_CCITT BIT24 #define MPSC_TX_REVERSE_DATA_MODE BIT28#define MPSC_RX_REVERSE_DATA_MODE BIT29#define MPSC_GLITCH_DETECT_ENABLE BIT31/* End of MMCRLx defines *//* main configuration register high - MMCRHx *//* set MMCRH for a given port (use MMCRH defines) */ #define GT_MPSC_MMCRH_CONFIG(port, MmcrhConfig) \ GT_REG_WRITE(MPSC_MAIN_CONFIG_HIGH(port), MmcrhConfig) #define MPSC_TRANSMIT_CLOCK_INVERT BIT0#define MPSC_TRANSMIT_BIT_STREAM_INVERSION BIT1#define MPSC_TRANSMIT_PREAMBLE_LENGTH_1B BIT2#define MPSC_TRANSMIT_PREAMBLE_LENGTH_2B BIT3#define MPSC_TRANSMIT_PREAMBLE_LENGTH_4B (BIT2|BIT3)#define MPSC_TRANSMIT_PREAMBLE_LENGTH_6B BIT4#define MPSC_TRANSMIT_PREAMBLE_LENGTH_8B (BIT2|BIT4)#define MPSC_TRANSMIT_PREAMBLE_LENGTH_16B (BIT3|BIT4)#define MPSC_TRANSMIT_CLOCK_DEVIDER_1x 0#define MPSC_TRANSMIT_CLOCK_DEVIDER_8x BIT9#define MPSC_TRANSMIT_CLOCK_DEVIDER_16x BIT10#define MPSC_TRANSMIT_CLOCK_DEVIDER_32x (BIT9|BIT10)#define MPSC_TRANSMIT_ENCODER_NRZ 0#define MPSC_TRANSMIT_ENCODER_NRZI BIT11 #define MPSC_TRANSMIT_ENCODER_FM0 BIT12#define MPSC_TRANSMIT_ENCODER_MANCHESTER BIT13#define MPSC_TRANSMIT_ENCODER_DIF_MANCHESTER (BIT12|BIT13)#define MPSC_RECEIVE_BIT_STREAM_INVERSION BIT16/* BIT22 MUST be set in Bisync and Uart and MUST not be set in HDLC mode */#define MPSC_RECEIVE_DATA_WIDTH_8BIT BIT22 #define MPSC_RECEIVE_DATA_WIDTH_16BIT 0 #define MPSC_RECEIVE_SYNC_LENGTH_4_BIT BIT23 #define MPSC_RECEIVE_SYNC_LENGTH_8_BIT BIT24#define MPSC_RECEIVE_SYNC_LENGTH_16_BIT (BIT23|BIT24)#define MPSC_RECEIVE_CLOCK_DEVIDER_1x 0#define MPSC_RECEIVE_CLOCK_DEVIDER_8x BIT25#define MPSC_RECEIVE_CLOCK_DEVIDER_16x BIT26#define MPSC_RECEIVE_CLOCK_DEVIDER_32x (BIT25|BIT26)#define MPSC_RECEIVE_ENCODER_NRZ 0#define MPSC_RECEIVE_ENCODER_NRZI BIT27 #define MPSC_RECEIVE_ENCODER_FM0 BIT28#define MPSC_RECEIVE_ENCODER_MANCHESTER BIT29#define MPSC_RECEIVE_ENCODER_DIF_MANCHESTER (BIT28|BIT29)#define MPSC_SYNCHRONIZE_ON_FALLING_AND_RISING 0 #define MPSC_SYNCHRONIZE_ON_RISING_EDGE BIT30 #define MPSC_SYNCHRONIZE_ON_FALLING_EDGE BIT31#define MPSC_NO_ADJUSTMENT_TO_CLOCK (BIT30|BIT31)/* Define the numer of bits to shift the fileds */#define MPSC_GDW_SHIFT 17#define MPSC_TPPT_SHIFT 5/* Fix the GDW shift of bit's */#define GT_MPSC_GDW(value) (((value) & 0xf) << MPSC_GDW_SHIFT)/* Fix the TPPT shift of bit's */#define GT_MPSC_TPPT(value) (((value) & 0xf) << MPSC_TPPT_SHIFT) /* End of MMCRHx defines*//***************************************************************************** HDLC DEFINITIONS****************************************************************************//* MPSCx Protocol Configuration Register (MPCRx) for HDLC */#define MPSC_HDLC_LOCAL_TALK BIT2#define MPSC_HDLC_CRC_COMPATIBLE_MODE 0#define MPSC_HDLC_CRC_COMPLIANCE_MODE BIT4#define MPSC_HDLC_DISABLE_RX_ON_TX BIT6#define MPSC_HDLC_COLLISION_MODE BIT9/* Bits' shift to NOF field */ #define MPSC_HDLC_NOF_SHIFT 12/* Set NOF field */#define GT_MPSC_HDLC_NUMBER_OF_FLAGS(value) \ (((value) & 0xf) << MPSC_HDLC_NOF_SHIFT) /* End of MPCR defines *//* Channel Register CHR1 for HDLC */#define MPSC_HDLC_DEFAULT_SYNC_CHAR 0x7E#define MPSC_HDLC_DEFAULT_ABORT_CHAR 0xFE/* Bits' shift to Abort field */ #define MPSC_HDLC_ABORT_SHIFT 16/* Set SYNC field */#define GT_MPSC_HDLC_SYNC(value) ((value) & 0xff)/* Set Abort field */#define GT_MPSC_HDLC_ABORT(value) (((value) & 0xff) << MPSC_HDLC_ABORT_SHIFT) /* End of CHR1 defines *//* Channel Register CHR2 for HDLC */#define MPSC_HDLC_ABORT_TX BIT7#define MPSC_HDLC_ABORT_RX BIT23#define MPSC_HDLC_ENTER_HUNT BIT31/* End of CHR2 defines *//* Channel Register CHR3 for HDLC *//* Set Max Frame Length field */#define GT_MPSC_HDLC_FRAME_LENGTH(value) ((value) & 0xffff)/* End of CHR3 defines *//* Channel Register CHR4 for HDLC */#define MPSC_HDLC_NULL_ENABLE BIT29#define MPSC_HDLC_BROADCAST_ENABLE BIT31/* set BCE field */#define GT_MPSC_HDLC_BCE_BITS(value) ((value) & 0xffff)/* End of CHR4 defines *//* Channel Register CHR5 for HDLC *//* set SHFR field */#define GT_MPSC_HDLC_SHORT_FRAME(value) ((value) & 0x7)/* End of CHR5 defines *//* Channel Register CHR6 for HDLC *//* bits' shift to AD2 field */#define MPSC_HDLC_ADDRESS_2_SHIFT 16/* set AD1 field */#define GT_MPSC_HDLC_RX_ADDR_RECOGNITION_1(value) ((value) & 0xffff)/* set AD2 field */#define GT_MPSC_HDLC_RX_ADDR_RECOGNITION_2(value) \ (((value) & 0xffff) << MPSC_HDLC_ADDRESS_2_SHIFT) /* End of CHR6 defines *//* Channel Register CHR7 for HDLC *//* bits' shift to AD4 field */#define MPSC_HDLC_ADDRESS_4_SHIFT 16/* set AD3 field */#define GT_MPSC_HDLC_RX_ADDR_RECOGNITION_3(value) ((value) & 0xffff)/* set AD4 field */#define GT_MPSC_HDLC_RX_ADDR_RECOGNITION_4(value) \ (((value) & 0xffff) << MPSC_HDLC_ADDRESS_4_SHIFT) /* End of CHR7 defines *//* Channel Register CHR10 for HDLC */#define MPSC_HDLC_CLEAR_TO_SEND BIT0#define MPSC_HDLC_CARRIER_DETECT BIT1#define MPSC_HDLC_TX_IN_IDLE BIT3#define MPSC_HDLC_RX_IN_HUNT BIT5#define MPSC_HDLC_RX_IN_IDLE BIT11#define MPSC_HDLC_DPLL_CARRIER_SENS BIT12#define MPSC_HDLC_RX_RECEIVING_FLAGS BIT13/* End of CHR10 defines *//***************************************************************************** BISYNC DEFINITIONS****************************************************************************//* MPSCx Protocol Configuration Register (MPCRx) for BISYNC */#define MPSC_BISYNC_AUTO_TRANSPARENT_MODE BIT2#define MPSC_BISYNC_DISABLE_RX_ON_TX BIT6#define MPSC_BISYNC_TRAILING_PAD BIT10#define MPSC_BISYNC_RX_TRANSPARENT_MODE BIT13#define MPSC_BISYNC_RX_DISCARD_BCC BIT14#define MPSC_BISYNC_TX_32_SYNC_MODE BIT15/* End of MPCRx defines *//* Channel Register CHR1 for BISYNC */#define MPSC_BISYNC_DISCARD_SYNC BIT15#define MPSC_BISYNC_DISCARD_DLE BIT31/* bits' shift to DLE field */#define MPSC_BISYNC_DLE_SHIFT 16/* set SYNC field */#define GT_MPSC_BISYNC_SYNC(value) ((value) & 0xff)/* set DLE field */#define GT_MPSC_BISYNC_DLE(value) (((value) & 0xff) << MPSC_BISYNC_DLE_SHIFT) /* End of CHR1 defines *//* Channel Register CHR2 for BISYNC */#define MPSC_BISYNC_TX_ENABLE_LONGITUDINAL_CHECK BIT0#define MPSC_BISYNC_TX_ENABLE_VERTICAL_PARITY_CHECK BIT1#define MPSC_BISYNC_TX_PARITY_ODD 0#define MPSC_BISYNC_TX_PARITY_LOW BIT2#define MPSC_BISYNC_TX_PARITY_EVEN BIT3#define MPSC_BISYNC_TX_PARITY_HIGH (BIT3 | BIT2)#define MPSC_BISYNC_TX_LONGITUDINAL_MODE_ODD 0#define MPSC_BISYNC_TX_LONGITUDINAL_MODE_EVEN BIT4#define MPSC_BISYNC_ABORT_TX BIT7#define MPSC_BISYNC_RX_ENABLE_LONGITUDINAL_CHECK BIT16#define MPSC_BISYNC_RX_ENABLE_VERTICAL_PARITY_CHECK BIT17#define MPSC_BISYNC_RX_PARITY_ODD 0#define MPSC_BISYNC_RX_PARITY_LOW BIT18#define MPSC_BISYNC_RX_PARITY_EVEN BIT19#define MPSC_BISYNC_RX_PARITY_HIGH (BIT19 | BIT18)#define MPSC_BISYNC_RX_LONGITUDINAL_MODE_ODD 0#define MPSC_BISYNC_RX_LONGITUDINAL_MODE_EVEN BIT20#define MPSC_BISYNC_ABORT_RX BIT23#define MPSC_BISYNC_CLOSE_RX_DESCRIPTOR BIT25#define MPSC_BISYNC_RESET_BCC BIT29#define MPSC_BISYNC_ENTER_HUNT BIT31/* End of CHR2 defines *//* Channel Register CHR4 for BISYNC *//* set BCE field */#define GT_MPSC_BISYNC_CONTROL_FILTERING(value) ((value) & 0xff)/* End of CHR4 defines */ /* Channel Registers CHR5-8 for BISYNC */#define MPSC_BISYNC_START_OF_HEADER BIT9#define MPSC_BISYNC_START_OF_TEXT BIT10#define MPSC_BISYNC_IGNORE_CHAR_IN_TEXT_MODE BIT11#define MPSC_BISYNC_GENERATE_INTERRUPT_ON_RX BIT12#define MPSC_BISYNC_MOVE_TO_HUNT BIT13#define MPSC_BISYNC_BCC_NEXT BIT14#define MPSC_BISYNC_ENTRY_NOT_VALID 0#define MPSC_BISYNC_ENTRY_VALID BIT15/* Const for BISYNC comm with none parity */#define MPSC_START_OF_TXT 0x2#define MPSC_END_OF_TXT 0x3#define MPSC_START_OF_HNDLR 0x1⌨️ 快捷键说明
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