gtmpsc.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* gtMpsc.h - Header File for Discovery MPCS functions.  */

/**************************************************************************
 *
 *   Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights
 *   reserved.  This Source Code is the Property of Curtiss-Wright
 *   Controls, Inc. and can only be used in accordance with Source
 *   Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any
 *   of its subsidiaries.
 *
 **************************************************************************/

/*******************************************************************************
*                   Copyright 2002, GALILEO TECHNOLOGY, LTD.                   *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*                                                                              *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
********************************************************************************/

/*
modification history
--------------------      
01d,08dec05,tis       rename Discovery_II directory to Discovery_III CR#12835.
01c,04may03,aak	      integrate into VME-182 BSP rel 0.0
01b,24oct02,aak	      integrate into VME-181 BSP rel 1.2
01a,26sep01,marvell   gtMpsc.h EV-64260A-BP BSP Version 2.2/1
*/

/*
* DESCRIPTION:
*       Header file for MPCS functions.
*       The header defines are gruoped in x different groups:
*       1. General for all protocols (with defines for fields in mpsc registers
*          - use reg's name to find it's defines)
*       2. Specific defines for HDLC, BISYNC, UART and Transparent (Mainly 
*          defines for fields in MPCR and CHRs).           
*       3. BRG defines.

DEPENDENCIES: 

*/

#ifndef _INCgtmpsch 
#define _INCgtmpsch

/* includes */
#if defined (SCP_124) || defined (VME_183)
#include "h/drv/discovery_III/sio/brg_dy4.h" 
#else
#include "h/drv/discovery_II/sio/brg_dy4.h" 
#endif
/* typedefs */
typedef enum _mpscPort {MPSC0
                       ,MPSC1
#ifdef INCLUDE_MPSC_PORTS_2_7
                       ,MPSC2
                       ,MPSC3
                       ,MPSC4
                       ,MPSC5
                       ,MPSC6
                       ,MPSC7
#endif /* INCLUDE_MPSC_PORTS_2_7 */
                       } MPSC_PORT;

typedef enum _mpscProtocol {HDLC, 
                            BISYNC, 
                            H_BISYNC, 
                            UART, 
                            TRANSPARENT
                           } MPSC_PROTOCOL_TYPE;

typedef enum _mpscClockSource {BRG0_SRC = 0
                               ,BRG1_SRC = 1
#ifdef INCLUDE_MPSC_PORTS_2_7
                               ,BRG2_SRC = 2
                               ,BRG3_SRC = 3
                               ,BRG4_SRC = 4
                               ,BRG5_SRC = 5
                               ,BRG6_SRC = 6
                               ,BRG7_SRC = 7
#endif /* INCLUDE_MPSC_PORTS_2_7 */
                               ,SCLK_SRC = 8
                               ,TSCLK_SRC = 9
                               ,NO_SRC = 0xf
                              } MPSC_CLOCK_SOURCE;
typedef enum _mpscBRGNumber {BRG0
                             ,BRG1
#ifdef INCLUDE_MPSC_PORTS_2_7
                             ,BRG2
                             ,BRG3
                             ,BRG4
                             ,BRG5
                             ,BRG6
                             ,BRG7
#endif /*INCLUDE_MPSC_PORTS_2_7*/
                            } MPSC_BRG_NUM;
/*
typedef enum _mpscbrgClockSource {BCLK_IN = 0, SCLK0 = 2, TSCLK0 = 3,
                                  SCLK1 = 6, TSCLK1 = 7, GT_TCLK = 8
                                 } MPSC_BRG_CLOCK_SOURCE;
*/
#define MPSC_BRG_CLOCK_SOURCE BRG_CLK_SRC

#if 0
typedef enum _mpscBisyncMode {BISYNC_NORMAL, BISYNC_TRANSPARENT, 
                              BISYNC_AUTO_TRANSPARENT
                             } MPSC_BISYNC_MODE;
typedef enum _mpscBisyncParityMode {PARITY_NONE, PARITY_EVEN, PARITY_ODD,
                                    PARITY_HIGH, PARITY_LOW
                                   } MPSC_BISYNC_PARITY_MODE;
#endif

/* struct returned by gtMpscConfigFor*protocol* functions */
typedef struct _mpscActualRates
{   
    unsigned int    rxClkActualRate; 
    unsigned int    txClkActualRate; 
} MPSC_ACTUAL_RATES;
                                            
/* defines */
#define     CRC_MODE_16_CCITT   0
#define     CRC_MODE_16         1
#define     CRC_MODE_32_CCITT   2

/* 181 to 182 porting defines 
#ifdef VME_182 */
#define SDMA_CAUSE SDMA_CAUSE_REG
#define SDMA_MASK  SDMA_MASK_REG

#define MPSC0_CAUSE			MPSC_CAUSE_REG(0)
#define MPSC1_CAUSE			MPSC_CAUSE_REG(1)
#define MPSC0_MASK			MPSC_MASK_REG(0)
#define MPSC1_MASK			MPSC_MASK_REG(1)
#define CHANNEL0_REGISTER1			MPSC_CHANNEL_REG1(0)
/* #endif */ 
/*******************************************************************************
*
*			GENERAL FOR ALL PROTOCOLS
*
*******************************************************************************/

/* Gap between mpsc registers */
/* Consts in use of all protocol */
#define	 MPSC_DEFAULT_NULL_VALUE		            0x0
#define  MPSC_DEFAULT_ALL_1				            0xffff

/* Connect port to serial controller - must do before using port */
#define GT_MPSC_MRR_CONFIG(port) GT_RESET_REG_BITS(MPSC_MAIN_ROUTING_REG,      \
                                              (BIT2 | BIT1 | BIT0) << (port*6));
                       
/* Define source for rx and tx clocks for a given port (use MPSC_CLOCK_SOURCE
   to define sources) */
#define GT_MPSC_CLOCK_ROUTING_CONFIG(port, rxSrc, txSrc)                       \
            GT_REG_WRITE(MPSC_RECEIVE_CLOCK_ROUTING_REG,                       \
                 GTREGREAD(MPSC_RECEIVE_CLOCK_ROUTING_REG) | (rxSrc << port*8));                                   \
            GT_REG_WRITE(MPSC_TRANSMIT_CLOCK_ROUTING_REG,                      \
                 GTREGREAD(MPSC_TRANSMIT_CLOCK_ROUTING_REG) | (txSrc << port*8))  
                                                         
/* Abort MPSC RX immediately */
#define GT_MPSC_ABORT_RX(port)                                                 \
                      GT_REG_WRITE(MPSC_CHANNEL_REG_2(port), MPSC_HDLC_ABORT_RX)  
            /* good for all protocols!!! */

/* Abort MPSC TX immediately */
#define GT_MPSC_ABORT_TX(port)                                                 \
                      GT_REG_WRITE(MPSC_CHANNEL_REG_2(port), MPSC_HDLC_ABORT_TX)  
            /* good for all protocols!!! */

/* Set MPCR for a given port (use MPCR defines, according to protocol) */                       
#define GT_MPSC_MPCR_CONFIG(port, MpcrConfig)						           \
			                GT_REG_WRITE(MPSC_PROTOCOL_CONFIG(port), MpcrConfig)
		   
/* Set CHR1 for a given port (use CHR1 defines, according to protocol) */                       
#define GT_MPSC_CHR1_CONFIG(port, ChrConfig)						           \
			                   GT_REG_WRITE(MPSC_CHANNEL_REG_1(port), ChrConfig)

/* Set CHR2 for a given port (use CHR2 defines, according to protocol) */                       
#define GT_MPSC_CHR2_CONFIG(port, ChrConfig)						           \
                               GT_REG_WRITE(MPSC_CHANNEL_REG_2(port), ChrConfig)

/* set CHR3 for a given port (use CHR3 defines, according to protocol) */                       
#define GT_MPSC_CHR3_CONFIG(port, ChrConfig)						           \
                               GT_REG_WRITE(MPSC_CHANNEL_REG_3(port), ChrConfig)

/* set CHR4 for a given port (use CHR4 defines, according to protocol) */                       
#define GT_MPSC_CHR4_CONFIG(port, ChrConfig)						           \
                               GT_REG_WRITE(MPSC_CHANNEL_REG_4(port), ChrConfig)

/* set CHR5 for a given port (use CHR5 defines, according to protocol) */                       
#define GT_MPSC_CHR5_CONFIG(port, ChrConfig)								   \
                               GT_REG_WRITE(MPSC_CHANNEL_REG_5(port), ChrConfig)

/* set CHR6 for a given port (use CHR6 defines, according to protocol) */                       
#define GT_MPSC_CHR6_CONFIG(port, ChrConfig)								   \
                               GT_REG_WRITE(MPSC_CHANNEL_REG_6(port), ChrConfig)

/* set CHR7 for a given port (use CHR7 defines, according to protocol) */                       
#define GT_MPSC_CHR7_CONFIG(port, ChrConfig)								   \
                               GT_REG_WRITE(MPSC_CHANNEL_REG_7(port), ChrConfig)

/* set CHR8 for a given port (use CHR8 defines, according to protocol) */                       
#define GT_MPSC_CHR8_CONFIG(port, ChrConfig)						    	   \
                               GT_REG_WRITE(MPSC_CHANNEL_REG_8(port), ChrConfig)

/* set CHR9 for a given port (use CHR9 defines, according to protocol) */                       
#define GT_MPSC_CHR9_CONFIG(port, ChrConfig)								   \
                               GT_REG_WRITE(MPSC_CHANNEL_REG_9(port), ChrConfig)
            
/* main configuration register low - MMCRLx */
/*  set MMCRL for a given port (use MMCRL defines) */                       
#define GT_MPSC_MMCRL_CONFIG(port, MmcrlConfig)						           \
		                   GT_REG_WRITE(MPSC_MAIN_CONFIG_LOW(port), MmcrlConfig)
                           
#define MPSC_MODE_HDLC                                  0
#define MPSC_MODE_UART                                  BIT2
#define MPSC_MODE_BISYNC                                (BIT2|BIT0)
#define MPSC_MODE_TRANSPARENT_TRANSMITTER               BIT3
#define MPSC_MODE_TRANSPARENT_RECEIVER                  BIT4
#define MPSC_ENABLE_TRANSMIT                            BIT6
#define MPSC_ENABLE_RECEIVE                             BIT7
#define MPSC_LOOP_BACK_MODE                             BIT8
#define MPSC_ECHO_MODE                                  BIT9
#define MPSC_LOOP_BACK_AND_ECHO_MODE                    (BIT8|BIT9)
#define MPSC_NULL_MODEM                                 BIT10
#define MPSC_TRANSMITTER_SYNC_TO_RECEIVER               BIT12
#define MPSC_TRANSMIT_SENSE_0                           0
#define MPSC_TRANSMIT_SENSE_1                           BIT14
#define MPSC_TRANSMIT_SENSE_2                           BIT15
#define MPSC_TRANSMIT_SENSE_3                           (BIT14|BIT15)