gtmpscintcntrl.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* gtIntControl.h - Header File for GT-64x60 Interrupt controller driver  */

/**************************************************************************
 *
 *   Copyright (c) 2005 Curtiss-Wright Controls, Inc. All rights
 *   reserved.  This Source Code is the Property of Curtiss-Wright
 *   Controls, Inc. and can only be used in accordance with Source
 *   Code License Agreement(s) of Curtiss-Wright Controls, Inc. or any
 *   of its subsidiaries.
 *
 **************************************************************************/

/*******************************************************************************
*              (c), Copyright 2001, Marvell International Ltd.                 *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.   *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS, IMPLIED *
* OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.           *
********************************************************************************/
/*
modification history
--------------------
01f,08dec05, tis        -add support for SCP-124
                        -rename Discovery_II directory to Discovery_III CR#12835.
01e,28sep05, asu 	add support for CCA-149
01d,06may05, tis        add support for CCA-146
01c,19nov04, tis        -include gt644xx.h instead of gt64360r_dy4.h
                        -include boardName.h
01b,04feb02,aak		integrate into VME-181 BSP rel 0.2
01a,26sep01,marvell EV-64260A-BP BSP Version 2.2/1
*/

#ifndef _INCgtMpscIntCntrlh
#define _INCgtMpscIntCntrlh

/* includes */
#include "h/drv/dy4/boardName.h"

#if defined(CCA_145) || defined(CCA_146) || defined(CCA_149)
#include "h/drv/discovery_II/gt644xx.h"
#endif

#ifdef VME_182
#include "h/drv/discovery_II/gt64360r_dy4.h"
#endif

#if defined (SCP_124) || defined (VME_183)
#include "h/drv/discovery_III/gt644xx.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/* defines  */

/* The following definition describes a specific cause bit in Hex format. */

#define MPSC_RX_INT             BIT0    /* MPSCx Normal Rx Interrupt Summary Logical OR of (unmasked) bits 4-7 below.   */
#define MPSC_RX_ERR_INT         BIT1    /* MPSCx Rx Error Interrupt Summary, Logical OR of (unmasked) bits 8-11 below.  */ 
#define MPSC_RESERVED1_INT      BIT2    /* Reserved                                                                     */ 
#define MPSC_TX_ERR_INT         BIT3    /* MPSCx Tx Error Interrupt Summary, Logical OR of (unmasked) bits 13-15 below. */ 
#define MPSC_RX_LSC_INT         BIT4    /* MPSCx Rx Line Status Change (from to IDLE) 0x0                               */ 
#define MPSC_RX_HNT_INT         BIT5    /* MPSCx Rx Entered HUNT State 0x0                                              */ 
#define MPSC_RX_FSC_INT         BIT6    /* MPSCx Rx Flag Status Change (HDLC mode)                                      */ 
#define MPSC_RX_RCC_INT         BIT6    /* MPSCx Received Control Character (Bisync, Uart modes)                        */ 
#define MPSC_RX_CSC_INT         BIT7    /* MPSCx Rx Carrier Sense Change (DPLL decoded carri-ers sense)                 */ 
#define MPSC_RX_OVR_INT         BIT8    /* MPSCx Rx Overrun 0x0                                                         */ 
#define MPSC_RX_CDL_INT         BIT9    /* MPSCx Rx Carrier Detect Loss 0x0                                             */ 
#define MPSC_RX_CGLITCH_INT     BIT10   /* MPSCx Rx Clock Glitch 0x0                                                    */ 
#define MPSC_RX_BPERR_INT       BIT11   /* MPSCx Bisync Protocol Error (valid only in Bisync mode)                      */ 
#define MPSC_TX_EIDL_INT        BIT12   /* MPSCx Tx Entered IDLE State 0x0                                              */ 
#define MPSC_TX_UDR_INT         BIT13   /* MPSCx Tx Underrun 0x0                                                        */ 
#define MPSC_TX_CTSL_INT        BIT14   /* MPSCx Tx Clear To Send Loss 0x0                                              */ 
#define MPSC_TX_CGLITCH_INT     BIT15   /* MPSCx Tx Clock Glitch 0x0                                                    */ 
     
/* gtIntControl.h API list */
/*****************************************************************
* STATUS  gtMpscIntCauseEnable (UINT32 mpscChan, UINT32 intBit);
* STATUS  gtMpscIntCauseDisable (UINT32 mpscChan, UINT32 intBit);
* STATUS  gtMpscIntMaskEnable (UINT32 mpscChan, UINT32 intBit);
* STATUS  gtMpscIntMaskDisable (UINT32 mpscChan, UINT32 intBit);
*****************************************************************/

#ifdef __cplusplus
}
#endif

#endif   /* _INCgtMpscIntCntrlh */