📄 siody4drv.h

📁 Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码
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/* sioDy4Drv.h - generic definitions for the Dy 4 SA-Cap driver *//********************************************************************** * *   Copyright (c) 2003-2004, Dy 4 Systems All rights reserved. *   This Source Code is the Property of Dy 4 Systems Inc. and can *   only be used in accordance with Source Code License *   Agreement of Dy 4 Systems Inc. dba (doing business as)  *   CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING, "CWCEC".  * **********************************************************************//*modification history--------------------01b,28feb05,rcd - added LOOPBACK define.01a,22sep03,aak   create from z85230Drv.h rev.01c*/#ifndef SIODY4DRV_H#define SIODY4DRV_H/* Protocol Definitions *//* Asynchronous */#define SIO_DY4_ASYNC 100/* Raw HDLC */#define SIO_DY4_RHDLC 101/* * The sync/async serial driver uses the standard VxWorks functions * open, close, read, write, and ioctl to configure the serial device. */#define SIO_DY4_OPEN                 (SIO_OPEN)#define SIO_DY4_HUP                  (SIO_HUP)#define SIO_DY4_SET_MODE             (SIO_MODE_SET)#define SIO_DY4_GET_MODE             (SIO_MODE_GET)#define SIO_DY4_SET_BAUDRATE         (SIO_BAUD_SET)#define SIO_DY4_GET_BAUDRATE         (SIO_BAUD_GET)#define SIO_DY4_HW_OPTS_SET          (SIO_HW_OPTS_SET)#define SIO_DY4_HW_OPTS_GET          (SIO_HW_OPTS_GET)#define SIO_DY4_AVAIL_MODES_GET      (SIO_AVAIL_MODES_GET)/* * The driver defines a set of proprietary commands to enhance the device * configuration options. */#define SIO_DY4_IOCTL_BASE           (0x2000)#define SIO_DY4_SET_PROTOCOL         (SIO_DY4_IOCTL_BASE)#define SIO_DY4_SET_TXBUF_CAPACITY   (SIO_DY4_IOCTL_BASE + 1)#define SIO_DY4_GET_TXBUF_CAPACITY   (SIO_DY4_IOCTL_BASE + 2)#define SIO_DY4_SET_RXBUF_CAPACITY   (SIO_DY4_IOCTL_BASE + 3)#define SIO_DY4_GET_RXBUF_CAPACITY   (SIO_DY4_IOCTL_BASE + 4)#define SIO_DY4_SET_BLOCKING         (SIO_DY4_IOCTL_BASE + 5)#define SIO_DY4_GET_BLOCKING         (SIO_DY4_IOCTL_BASE + 6)#define SIO_DY4_SET_RXADDR           (SIO_DY4_IOCTL_BASE + 9)#define SIO_DY4_GET_RXADDR           (SIO_DY4_IOCTL_BASE + 10)#define SIO_DY4_SET_HALFDUPLEX       (SIO_DY4_IOCTL_BASE + 11)#define SIO_DY4_GET_HALFDUPLEX       (SIO_DY4_IOCTL_BASE + 12)#define SIO_DY4_SET_CHK_ADDR         (SIO_DY4_IOCTL_BASE + 13)#define SIO_DY4_GET_CHK_ADDR         (SIO_DY4_IOCTL_BASE + 14)#define SIO_DY4_SET_CHK_CRC          (SIO_DY4_IOCTL_BASE + 15)#define SIO_DY4_GET_CHK_CRC          (SIO_DY4_IOCTL_BASE + 16)#define SIO_DY4_SET_WRITE_TO         (SIO_DY4_IOCTL_BASE + 17)#define SIO_DY4_GET_WRITE_TO         (SIO_DY4_IOCTL_BASE + 18)#define SIO_DY4_SET_READ_TO          (SIO_DY4_IOCTL_BASE + 19)#define SIO_DY4_GET_READ_TO          (SIO_DY4_IOCTL_BASE + 20)#define SIO_DY4_SET_RXCLK_EXT       (SIO_DY4_IOCTL_BASE + 21)#define SIO_DY4_GET_RXCLK_EXT       (SIO_DY4_IOCTL_BASE + 22)#define SIO_DY4_SET_TXCLK_OFF_DELAY (SIO_DY4_IOCTL_BASE + 23)#define SIO_DY4_GET_TXCLK_OFF_DELAY (SIO_DY4_IOCTL_BASE + 24)#define SIO_DY4_SET_CRC_POLY         (SIO_DY4_IOCTL_BASE + 25)#define SIO_DY4_GET_CRC_POLY         (SIO_DY4_IOCTL_BASE + 26)#define SIO_DY4_FLUSH                (SIO_DY4_IOCTL_BASE + 43)#define SIO_DY4_LOOPBACK             (SIO_DY4_IOCTL_BASE + 44)/* transfer modes */#define SIO_DY4_MODE_INT            (0)#define SIO_DY4_MODE_DMA            (1)/* CRC Polynomials */#define SIO_DY4_POLY_SDLC      (0)    /* default */#define SIO_DY4_POLY_CRC16     (1)    #define SIO_DY4_POLY_SDLC32    (2) /* Dy 4 SA-Cap driver generic error codes */#define SIO_DY4_OK                        (OK)#define SIO_DY4_ERR                       (ERROR)#define SIO_DY4_ERR_BASE                  (1)#define SIO_DY4_ERR_OUT_OF_MEM            (SIO_DY4_ERR_BASE + 1)#define SIO_DY4_ERR_INVALID_PARAM         (SIO_DY4_ERR_BASE + 2)#define SIO_DY4_ERR_CHAN_OPEN             (SIO_DY4_ERR_BASE + 3)#define SIO_DY4_ERR_CHAN_CLOSED           (SIO_DY4_ERR_BASE + 4)#define SIO_DY4_ERR_RX_BUF_OVERFLOW       (SIO_DY4_ERR_BASE + 5)#define SIO_DY4_ERR_TX_BUF_UNDERFLOW      (SIO_DY4_ERR_BASE + 6)#define SIO_DY4_ERR_RX_OVERFLOW           (SIO_DY4_ERR_BASE + 7)#define SIO_DY4_ERR_TX_UNDERFLOW          (SIO_DY4_ERR_BASE + 8)#define SIO_DY4_ERR_INVALID_COMMAND       (ENOSYS)#define SIO_DY4_ERR_RX_FRAME_OVERFLOW     (SIO_DY4_ERR_BASE + 10)#define SIO_DY4_ERR_BAD_CRC               (SIO_DY4_ERR_BASE + 11)#define SIO_DY4_ERR_TIMEOUT               (SIO_DY4_ERR_BASE + 12)#define SIO_DY4_ERR_PARITY                (SIO_DY4_ERR_BASE + 13)#define SIO_DY4_ERR_EIO                   (EIO)#define SIO_DY4_ERR_ENOSYS                (ENOSYS)#define SIO_DY4_ERR_NOT_IMPLEMENTED       (SIO_DY4_ERR_BASE + 16)#define SIO_DY4_ERR_OPEN_FAILED           (SIO_DY4_ERR_BASE + 17)#endif /* SIODY4DRV_H */
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